Stackable ball grid array semiconductor package and fabrication method thereof

• US 20010048151A1
• Filed: 08/06/2001
• Published: 12/06/2001
• Est. Priority Date: 05/30/1998
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: SK Hynix Inc.
• Inventors: Chun, Dong Seok
• Granted Patent: US 6,407,448 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/73219 Layer and TAB connectors
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/055 the leads having a passage through the base H01L23/057 takes precedence
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A stackable Ball Grid Array (BGA) semiconductor chip package and a fabrication method thereof increases reliability and mount density of a semiconductor package. The stackable BGA semiconductor chip package includes a supporting member that includes a supporting plate and a supporting frame formed on edges of the supporting plate. Conductive patterns are formed in and extend through the supporting member. First metal traces are formed on a bottom of the supporting plate and the first metal traces are connected to first ends of the conductive patterns in the supporting member. Second metal traces are attached to an upper surface of a semiconductor chip, and the semiconductor chip is attached to the supporting member. The second metal traces are connected to bond pads of the chip, and to upper ends of the conductive patterns in the supporting member. A plurality of conductive balls are then attached to exposed portions of the first and/or the second metal traces.

Claims

1. A stackable chip package, comprising:

a supporting member having a plurality of conductive patterns formed therein;

a plurality of first conductive traces formed on a first surface of the supporting member, wherein respective ones first conductive traces are electrically coupled to corresponding ones of the conductive patterns;

a chip having chip pads, wherein the chip is attached to a second surface of the supporting member; and

a plurality of second conductive traces, wherein portions of the second conductive traces are arranged over the chip, and wherein respective ones of the second conductive traces are electrically coupled to corresponding ones of the chip pads and corresponding ones of the conductive patterns.

2. The stackable chip package of

claim 1

, wherein first ends of the second conductive traces are arranged over the chip, wherein middle portions of respective ones of the second conductive traces are electrically coupled to corresponding chip pads, and wherein second ends of respective ones of the second conductive traces are electrically coupled to corresponding ones of the conductive patterns.

3. The stackable chip package of

claim 1

, further comprising a solder resist covering portions of the plurality of first conductive traces, wherein the solder resist leaves connecting portions of the first conductive traces exposed.

4. The stackable chip package of

claim 3

, further comprising a plurality of conductive members, wherein respective ones of the conductive members are electrically coupled to corresponding ones of the connecting portions of the first conductive traces, and wherein the plurality of conductive members act as leads of the chip package.

5. The stackable chip package of

claim 1

, further comprising a solder resist covering portions of the plurality of second conductive traces, wherein the solder resist leaves connecting portions of the second conductive traces exposed.

6. The stackable chip package of

claim 5

, further comprising a plurality of conductive members, wherein respective ones of the conductive members are electrically coupled to corresponding ones of the connecting portions of the second conductive traces, and wherein the plurality of conductive members act as leads of the chip package.

7. The stackable chip package of

claim 6

, wherein the plurality of conductive members are arranged in an array over the chip.

8. The stackable chip package of

claim 1

, further comprising a molding resin that covers portions of the second conductive traces, and portions of the chip.

9. The stackable chip package of

claim 1

, wherein the supporting member comprises a supporting plate and a supporting frame formed at peripheral portions of the supporting plate.

10. The stackable chip package of

claim 9

, wherein the plurality of conductive patterns are formed in the supporting frame.

11. The stackable chip package of

claim 1

, further comprising an elastomer that attaches the plurality of second conductive traces to the chip.

12. The stackable chip package of

claim 11

, wherein an adhesive is interposed between the second conductive traces and the elastomer.

13. The stackable chip package of

claim 1

, wherein the plurality of first conductive traces are arranged on the first surface of the supporting member in substantially the same pattern as the plurality of second conductive traces are arranged over the chip.

14. A stackable chip package, comprising:

a supporting member having a plurality of conductive patterns formed therein;

a chip having chip pads, wherein the chip is attached to a upper surface of the supporting member;

a plurality of first conductive traces, wherein a first end of each first conductive trace is electrically coupled to a corresponding conductive pattern and a second end of each first conductive trace terminates below said chip;

a plurality of second conductive traces, wherein a first end of each second conductive trace terminates above said chip, a middle portion of each second conductive trace is electrically coupled to a corresponding chip pad, and a second end of each second conductive trace is electrically coupled to a corresponding conductive pattern.

15. The stackable chip package of

claim 14

, wherein said plurality of first conductive traces is formed on a lower surface of said supporting member.

16. The stackable chip package of

claim 14

, further comprising a solder resist covering portions of the plurality of first conductive traces, wherein the solder resist leaves connecting portions of the first conductive traces exposed.

17. The stackable chip package of

claim 16

, further comprising a plurality of conductive members, wherein respective ones of the conductive members are electrically coupled to corresponding ones of the connecting portions of the first conductive traces, and wherein the plurality of conductive members act as leads of the chip package.

18. The stackable chip package of

claim 14

, further comprising a solder resist covering portions of the plurality of second conductive traces, wherein the solder resist leaves connecting portions of the second conductive traces exposed.

19. The stackable chip package of

claim 18

, further comprising a plurality of conductive members, wherein respective ones of the conductive members are electrically coupled to corresponding ones of the connecting portions of the second conductive traces, and wherein the plurality of conductive members act as leads of the chip package.

20. The stackable chip package of

claim 19

, wherein the plurality of conductive members are arranged in an array over the chip.

21. The stackable chip package of

claim 14

, further comprising a molding resin that covers portions of the second conductive traces, and portions of the chip.

22. The stackable chip package of

claim 14

, wherein the supporting member comprises a supporting plate and supporting frame formed at peripheral portions of the supporting plate.

23. The stackable chip package of

claim 22

, wherein the plurality of conductive patterns are formed in the supporting frame.

24. The stackable chip package of

claim 14

, further comprising an elastomer that attaches the plurality of second conductive traces to the chip.

25. The stackable chip package of

claim 24

, wherein an adhesive is interposed between the second conductive traces and the elastomer.

26. The stackable chip package of

claim 14

, wherein the plurality of first conductive traces are arranged on the lower surface of the supporting member in substantially the same pattern as the plurality of second conductive traces are arranged over the chip.