Programmable glitch filter

• US 20010048341A1
• Filed: 05/24/2001
• Published: 12/06/2001
• Est. Priority Date: 05/29/2000
• Status: Active Grant

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Chakravarthy, Kalyana
• Granted Patent: US 6,535,057 B2
• Time in Patent Office: Days
• US Class Current: 327/551
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08

Abstract

A glitch filter includes a storage element for storing a current state, which is the output of the filter. An output of the storage element is connected to one input of a state comparator. Another input of the state comparator is connected to an input signal. A programmable clock delay is connected between the state comparator and the storage element. The programmable clock delay may provide a programmed duration independent of the technology used for implementation. The glitch filter is arranged such that the input signal is stored as the new current state in the storage element only if the input signal changes and then remains unchanged for the programmed duration.

Claims

1. A glitch filter comprising:

a storage means for storing a current state, which is the output of the said filter,

the output of said storage means is connected to one input of a state comparator and the other input of the said state comparator is connected to the input signal,

a programmable clock delay means for any required duration which is independent of technology of implementation, is connected between the said state comparator and said storage means,

the arrangement being such that the input signal is stored as the new current state in the said storage means only if the input signal changes and then remains unchanged for the programmed duration.

2. A glitch filter as claimed in

claim 1

wherein the said means for providing a programmable clock delay comprising:

a counter for counting clock pulses to provide a time delay, the control input of the said counter being connected to the output of the said state comparator,

the output of the said counter is connected to one input of a digital delay comparator, the other input of the said delay comparator receives a digital value corresponding to the maximum glitch width to be filtered,

the output of the said delay comparator is connected to the input of the said storage means.

3. A glitch filter as claimed in

claim 2

wherein the counter is enabled only if the input to the said glitch filter is not equal to the output of said storage means and the said counter is initialized when the input of the said glitch filter is equal to the output of said storage means

4. A glitch filter as claimed in

claim 1

wherein a multiplexer is provided at the output of the said storage means, which also receives the input signal at its other input and the programmable digital value for the desired maximum glitch width at its control input, the arrangement being such that when the programmed digital value is zero, the input signal is fed to the output of the multiplexer and when the value is not zero, the storage means output is fed to the output of the multiplexer.

5. A glitch filter as claimed in

claim 2

wherein the number of bits used for the said counter and said digital delay comparator depends upon the desired range of programmable digital values for maximum glitch width.

6. A method for filtering glitches comprising:

storing a current state, which is the final output,

comparing the said current state with the input signal,

enabling a programmable delay whenever the input signal is different from the stored current state and initializing the programmable delay whenever the input signal is same as the stored current state,

making the stored current state equal to the input signal if the programmed delay is complete.

7. A method as claimed in

claim 6

wherein programmable delay is obtained by:

counting clock pulses

comparing the counted clock pulses with a digital value corresponding to the maximum glitch width,

generating a signal indicating completion of programmed delay when the counted clock pulses become equal to the said digital value.

8. A method as claimed in

claim 7

wherein the counting is enabled only if the input signal is not equal to the stored output state and counting is initialized whenever the input signal is equal to the stored output state.

9. A method as claimed in

claim 6

wherein the filtering of glitches is enabled only when the digital value for desired glitch width is non-zero and is disabled when the digital value is zero.