Method and apparatus for processing a secondary synchronization channel in a spread spectrum system

• US 20010048714A1
• Filed: 01/29/2001
• Published: 12/06/2001
• Est. Priority Date: 01/28/2000
• Status: Abandoned Application

• Current Assignee: MorphICs Technology, Inc. (Infineon Technologies AG)
• Original Assignee: MorphICs Technology, Inc. (Infineon Technologies AG)
• Inventors: Jha, Uma
• Application Number:
  US09/772,583
• Publication Number:
  US 20010048714A1
• Time in Patent Office: Days
• US Class Current: 375/150
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/70735 Code identification H04B1/7083 takes precedence
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/709 Correlator structure

Abstract

A method and apparatus for processing a secondary synchronization channel in a spread spectrum system is disclosed herein. The method includes several steps, the first of which is to receive a first input data at a correlator. Next, a first code sequence of a code group is received at the correlator. The first correlator then correlates the first input data with the first code sequence. Afterward, a second code sequence is received at the correlator. This time, the first input data is correlated with the second code sequence. Correlation of both the first code sequence and the second code sequence occurs prior to receiving a second input data. Lastly, correlation results from the first correlator are compared with a threshold value using a threshold detector.

Claims

1. A method of correlating multiple code groups against input data, the method comprising the steps of:

a) receiving a first input data at a first correlator;

b) receiving a first code sequence of a code group at the first correlator;

c) correlating the first input data with the first code sequence using the correlator;

d) receiving a second code sequence at the first correlator;

e) correlating the first input data with the second code sequence using the first correlator, wherein correlating step e) is performed prior to receiving a second input data; and

f) comparing a correlation result from the first correlator with a threshold value using a first threshold detector.

2. The method recited in

claim 1

wherein the first input data and the second input data are synchronization sequence inputs, and wherein the first code sequence and the second code sequence are locally stored scrambling sequences.

3. The method recited in

claim 1

further comprising the steps of:

g) receiving in parallel the first input data at a second correlator with respect to the first correlator;

h) receiving a third code sequence at the second correlator;

i) correlating in parallel the first input data with the third code sequence using the second correlator, with respect to the first correlator; and

j) comparing a correlation result from the second correlator with the threshold value using a second threshold detector.

4. The method recited in

claim 3

further comprising the steps of:

k) receiving a fourth code sequence at the second correlator; and

l) correlating the first input data with the fourth code sequence using the second correlator, wherein correlating step k) is performed prior to receiving the second input data.

5. The method recited in

claim 1

further comprising the steps:

g) repeating steps a) through f) for additional code sequences as defined by a communication protocol.

6. The method recited in

claim 4

further comprising the step of:

m) repeating steps a) through l) for additional code sequences as defined by a communication protocol.

7. The method recited in

claim 1

further comprising the step of:

g) receiving configuration information at the first correlator.

8. The method recited in

claim 1

further comprising the step of:

g) scaling a system clock rate into a local clock rate, wherein the local clock rate ranges from a slot period to a fraction of the slot period.

9. A method for configuring a configurable searcher, the method comprising the steps of:

a) receiving a code group configuration input at a communication device.

b) communicating the code group configuration to the configurable searcher;

c) initializing the configurable searcher according to the code group configuration; and

d) operating the configurable searcher according to the code group configuration.

10. The method recited in

claim 9

further comprising the steps of:

e) storing the code group configuration in memory.

11. The method recited in

claim 9

wherein the code group configuration input specifies a quantity of groups of codes, an order of code sequences within each group, or the sequence values.

12. The method recited in

claim 11

further comprising the step of:

e) allocating a sufficient memory to accommodate the quantity of code groups and a length of the sequences used in code groups.

13. The method recited in

claim 9

further comprising the step of:

e) receiving a local clock rate input at which the configurable searcher is to operate; and

14. The method recited in

claim 9

further comprising the step of:

e) identifying a quantity of correlators necessary for accommodating a code group configuration.

15. The method recited in

claim 9

further comprising the step of:

e) modifying a system clock rate at a local controller to match a local clock rate input.

16. The method recited in

claim 13

further comprising the step of:

f) operating the configurable searcher according to the code group configuration and the local clock rate input.

17. A searcher for data processing, the searcher comprising:

a first input line for communicating input data;

a second input line for communicating a first set of code sequences;

a first correlator coupled to the first input line and the second input line, the first correlator circuit capable of completing a correlation operation within a fraction of a slot period; and

a first threshold detector coupled to the first correlator, the first threshold detector receiving a threshold input and a correlation result from the first correlator.

18. The searcher recited in

claim 17

further comprising:

a first memory coupled to the second input line, the first memory storing the first set of code sequences.

19. The searcher recited in

claim 17

further comprising:

a third input line for communicating a second set of code sequences;

a second correlator coupled to the first input line in parallel to the first correlator, wherein the second correlator coupled to the third input line, and wherein the second correlator is capable of completing a correlation operation within the fraction of the slot period;

a second threshold detector coupled to the second correlator, the second threshold detector receiving the threshold input and a correlation result from the second correlator.

20. The searcher recited in

claim 19

further comprising:

a second memory coupled to the third input line, the second memory storing the second set of code sequences.

21. The searcher recited in

claim 19

further comprising:

a local controller capable of scaling a system clock rate into a local clock rate that ranges from the slot period to the fraction of the slot period.

22. A communication device for processing a data signal, the communication device comprising:

a front-end processor for communicating the data signal;

a processor coupled to the front-end processor and a modem;

a system memory coupled to the processor;

a configurable searcher system coupled to the processor, the configurable searcher system using a code group configuration dictated by a desired one of a plurality of communication protocols; and

wherein the processor and the system memory provide configuration information to the configurable searcher system.

23. The communication device recited in

claim 22

wherein the configurable searcher system comprises:

a configurable searcher;

a local memory coupled to the configurable searcher, the local memory capable of storing the configuration information.

24. The communication device recited in

claim 23

wherein the configurable searcher system further comprises:

a local controller coupled to the local memory and to the configurable searcher, the local controller scaling a system clock rate to match a local clock rate.