Method of manufacturing a trench mosfet using selective growth epitaxy

• US 20010049167A1
• Filed: 02/09/2001
• Published: 12/06/2001
• Est. Priority Date: 06/05/2000
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Madson, Gordon K.
• Granted Patent: US 6,635,534 B2
• Time in Patent Office: Days
• US Class Current: 438/212
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of manufacturing a trench structure for a trench MOSFET, including the steps of providing a semiconductor substrate having a major surface, forming a dielectric pillar on the substrate major surface (the dielectric pillar extending substantially perpendicularly from the major surface of the substrate), selectively forming a semiconductor layer around the dielectric pillar, and removing a predetermined length of the dielectric pillar to create a trench in the substrate, the trench defined by sidewalls and a bottom. The method permits the controlled formation of a dielectric plug at the bottom of the trench, the plug having predetermined dimensions.

Claims

1. A method of forming a trench structure, the method comprising the steps of:

providing a semiconductor substrate having a major surface;

forming a dielectric pillar on the substrate major surface, the dielectric pillar extending substantially perpendicularly from the major surface;

selectively forming a semiconductor layer around the dielectric pillar; and

removing a predetermined length of the dielectric pillar to create a trench in the substrate, the trench defined by sidewalls and a bottom.

2. The method of

claim 1

, wherein a dielectric plug, of a predetermined thickness is left at the bottom of the trench, following the step of removing a predetermined length of the dielectric pillar.

3. The method of

claim 2

, further comprising the step of forming an oxide layer on the sidewalls of the trench.

4. The method of

claim 1

, wherein the semiconductor layer is formed using selective epitaxial growth.

5. A method of manufacturing a trench field effect transistor, comprising the steps of:

providing a semiconductor substrate having a major surface and a first conductivity type;

forming a plurality of dielectric columns extending perpendicularly from the major surface of the substrate;

selectively forming a first semiconductor layer having the first conductivity type over exposed areas of the major surface of the substrate and around the dielectric columns;

selectively forming a second semiconductor layer having a second conductivity type, opposite to that of the first conductivity type, over the first semiconductor layer and around the dielectric columns;

selectively forming a third semiconductor layer having the first conductivity type over the second semiconductor layer and around the semiconductor columns;

removing a predetermined portion of each dielectric column to create a plurality of trenches extending through the third, second and a portion of the first semiconductor layer, each trench defined by a bottom and sidewalls; and

lining the sidewalls of the trenches with a gate oxide.

6. The method of

claim 5

, wherein the step of lining the sidewalls of the trenches further comprises forming a pad oxide layer on a horizontal surface of the third semiconductor layer.

7. The method of

claim 6

, further comprising the step of filling the gate-oxide-lined trenches with a conductive material to form a gate for the transistor.

8. The method of

claim 7

, further comprising the step of forming a nitride mask over the pad oxide layer.

9. The method of

claim 8

, further comprising the step of selectively removing a portion of each of the pad oxide and nitride layers in regions above each conductive-material-filled trench.

10. The method of

claim 9

, further comprising the step of forming a dielectric cap over each conductive-material-filled trench.

11. The method of

claim 10

, further comprising the step of forming a heavy body having the second conductivity type within the third semiconductor layer and partially within the second semiconductor layer, wherein a doping concentration of the heavy body is greater than a doping concentration of the second semiconductor layer.

12. The method of

claim 7

, further comprising the step of etching back the conductive material to a predetermined recess within the trenches.

13. The method of

claim 12

, further comprising the step of removing the pad oxide layer.

14. The method of

claim 13

, further comprising the step of forming a blanket dielectric layer over the openings of the trenches and over the exposed portions of the third semiconductor layer.

15. The method of

claim 14

, wherein the blanket dielectric layer is formed by way of thermal oxidation of exposed portions of conductive material and exposed portions of the third semiconductor layer.

16. The method of

claim 15

, further comprising the step of removing a portion of the blanket dielectric layer to leave dielectric caps over the trenches, which extend partially into the third semiconductor layer.

17. The method of

claim 16

, further comprising the step of selectively forming a fourth semiconductor layer having the first conductivity type over the third semiconductor layer and around the dielectric caps.

18. The method of

claim 17

, further comprising the step of forming a heavy body having the second conductivity type within the third and fourth semiconductor layers and partially within the second semiconductor layer, wherein a doping concentration of the heavy body is greater than a doping concentration of the second semiconductor layer.

19. The method of

claim 17

, wherein the step of forming a fourth semiconductor layer having the first conductivity type is controlled so that the resulting fourth semiconductor layer has an exposed surface that is substantially planar to exposed surfaces of the dielectric caps.

20. The method of

claim 19

, wherein the dielectric caps have lateral dimensions within the plane of the exposed surface of the dielectric caps that are approximately equal to lateral dimensions of the trenches in the same plane.