Lateral super-junction semiconductor device

• US 20010050394A1
• Filed: 04/27/2001
• Published: 12/13/2001
• Est. Priority Date: 04/27/2000
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Sato, Takahiro, Onishi, Yasuhiko, Iwamoto, Susumu, Fujihira, Tatsuhiko
• Granted Patent: US 6,756,636 B2
• Time in Patent Office: Days
• US Class Current: 257/343
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A lateral semiconductor device includes an alternating conductivity type layer for providing a first semiconductor current path in the ON-state of the device and for being depleted in the OFF-state of the device, that has an improved structure for realizing a high breakdown voltage in the curved sections of the alternating conductivity type layer.

Claims

1. A lateral semiconductor device comprising:

a semiconductor chip;

two main electrodes on one major surface of the semiconductor chip; and

an alternating conductivity type layer between the main electrodes;

wherein the alternating conductivity type layer comprises first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type;

wherein the first semiconductor regions and the second semiconductor regions are alternately arranged; and

wherein the alternating conductivity type layer comprises a closed loop surrounding one of the main electrodes.

2. The lateral semiconductor device according to

claim 1

, wherein the alternating conductivity type layer comprises first sections, wherein the first semiconductor regions and the second semiconductor regions are arranged alternately at a first pitch, and second sections, wherein the first semiconductor regions and the second semiconductor regions are arranged alternately at a second pitch different from the first pitch.

3. The lateral semiconductor device according to

claim 1

, wherein the alternating conductivity type layer comprises at least one straight section and at least one curved section.

4. The lateral semiconductor device according to

claim 3

, wherein the alternating conductivity type layer comprises at least two straight sections and at least two curved sections.

5. The lateral semiconductor device according to

claim 4

, wherein the alternating conductivity type layer comprises at least four straight sections and at least four curved sections.

6. The lateral semiconductor device according to

claim 3

, wherein the first semiconductor regions and the second semiconductor regions are arranged alternately at the first pitch in the straight sections, and the first semiconductor regions and the second semiconductor regions are arranged alternately at the second pitch in the curved sections.

7. The lateral semiconductor device according to

claim 6

, wherein the first pitch is equal to or longer than the second pitch.

8. The lateral semiconductor device according to

claim 6

, wherein the curved sections are doped substantially more lightly than the straight sections.

9. The lateral semiconductor device according to

claim 8

, wherein the curved sections are substantially intrinsic.

10. The lateral semiconductor device according to

claim 8

, wherein the first pitch is shorter than the second pitch.

11. The lateral semiconductor device according to

claim 8

, wherein the curved sections are doped with an n-type impurity and a p-type impurity.

12. The lateral semiconductor device according to

claim 9

, wherein the curved sections are doped with an n-type impurity and a p-type impurity.

13. The lateral semiconductor device according to

claim 3

, wherein the width of at least a portion of the curved section is larger than the width of the straight section.

14. The lateral semiconductor device according to

claim 1

, further comprising one or more closed loops, each including an alternating conductivity type layer.

15. The lateral semiconductor device according to

claim 1

, wherein the width of the first semiconductor region or the second semiconductor region is from ¼

to 4 times as large as the depth of the first semiconductor region or the second semiconductor region respectively.

16. The lateral semiconductor device according to

claim 1

, wherein the width of the alternating conductivity type layer is from 12.5 to 100 times as large as the width of the first semiconductor region or the second semiconductor region.

17. The lateral semiconductor device according to

claim 16

, wherein the width of the alternating conductivity type layer is from 12.5 to 100 times as large as the depth of the first semiconductor regions or the second semiconductor regions.

31. The lateral semiconductor device according to

claim 1

, wherein the lateral semiconductor device comprises a semiconductor device selected from the group consisting of a MOSFET, a bipolar transistor, an IGBT and a diode;

the main electrode, the potential thereof is high, is inside the closed loop; and

the other main electrode, the potential thereof is low, is outside the closed loop.

33. The lateral semiconductor device according to

claim 1

, further comprising a circuit for controlling the semiconductor device, for protecting the semiconductor device and for detecting the states of the semiconductor device, the circuit being outside the closed loop.

18. A lateral semiconductor device comprising:

a semiconductor chip having two major surfaces;

two main electrodes on one of the major surfaces of the semiconductor chip;

one or more alternating conductivity type layers between the main electrodes, each of the alternating conductivity type layers comprising first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type, the first semiconductor regions and the second semiconductor regions being arranged alternately, the first semiconductor regions provide a current path in the ON-state of the semiconductor device and are depleted in the OFF-state of the semiconductor device, and the second semiconductor regions are depleted in the OFF-state of the semiconductor device; and

lightly doped regions, the impurity concentrations thereof are substantially low;

wherein the one or more alternating conductivity type layers and the lightly doped regions being connected to each other to form a closed loop surrounding one of the main electrodes.

19. The lateral semiconductor device according to

claim 18

, wherein the closed loop comprises at least one straight section and at least one curved section.

20. The lateral semiconductor device according to

claim 19

, wherein the closed loop comprises at least two straight sections and at least two curved sections.

21. The lateral semiconductor device according to

claim 20

, wherein the closed loop comprises four or more straight sections and four or more curved sections.

22. The lateral semiconductor device according to

claim 19

, wherein the straight section comprises the alternating conductivity type layer and the curved section comprises the lightly doped region.

23. The lateral semiconductor device according to

claim 18

, wherein the surface portion of the lightly doped region is substantially intrinsic.

24. The lateral semiconductor device according to

claim 18

, wherein the lightly doped regions are doped with an n-type impurity and a p-type impurity.

25. The lateral semiconductor device according to

claim 19

, wherein the width of the curved section is larger than the width of the straight section.

26. The lateral semiconductor device according to

claim 18

, wherein the width of the lightly doped region is larger than the width of the alternating conductivity type layer.

27. The lateral semiconductor device according to

claim 18

, further comprising one or more closed loops, each including one or more alternating conductivity type layers and lightly doped regions.

28. The lateral semiconductor device according to

claim 18

, wherein the width of the first semiconductor region or the second semiconductor region is from ¼

to 4 times as large as the depth of the first semiconductor region or the second semiconductor region.

29. The lateral semiconductor device according to

claim 18

, wherein the width of the alternating conductivity type layer is from 12.5 to 100 times as large as the width of the first semiconductor region or the second semiconductor region.

30. The lateral semiconductor device according to

claim 18

, wherein the width of the alternating conductivity type layer is from 12.5 to 100 times as large as the depth of the first semiconductor regions or the second semiconductor regions.

32. The lateral semiconductor device according to

claim 18

, wherein the lateral semiconductor device comprises a semiconductor device selected from the group consisting of a MOSFET, a bipolar transistor, an IGBT and a diode;

the main electrode, the potential thereof is high, is inside the closed loop; and

the other main electrode, the potential thereof is low, is outside the closed loop.

34. The lateral semiconductor device according to

claim 18

, further comprising a circuit for controlling the semiconductor device, for protecting the semiconductor device and for detecting the states of the semiconductor device, the circuit being outside the closed loop.