Fuse programming circuit for programming fuses

• US 20010050406A1
• Filed: 06/06/2001
• Published: 12/13/2001
• Est. Priority Date: 06/09/2000
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Akita, Hironobu, Tsuchida, Kenji
• Granted Patent: US 6,438,059 B2
• Time in Patent Office: Days
• US Class Current: 257/529
• CPC Class Codes: H01L 27/0817 Thyristors only

Abstract

A fuse is programmed by being supplied with a current. The fuse is connected to a thyristor. A control circuit is connected to the gate of the thyristor. The control circuit turns the thyristor ON to allow the fuse to be programmed.

Claims

1. A fuse programming circuit comprising:

a fuse having first and second ends and programmed in accordance with a current supplied, the first end being connected to a first power supply;

a thyristor having first and second electrodes and a gate electrode, the first electrode being connected to the second end of the fuse and the second electrode being connected to a second power supply lower in potential than the first power supply; and

a control circuit having an input terminal supplied with an input signal and an output terminal connected to the gate electrode of the thyristor, the control circuit generating a control signal in accordance with the input signal which is supplied to the gate electrode of the thyristor to turn the thyristor ON.

2. A circuit according to

claim 1

, wherein the fuse is comprised of a fuse whose current path is cut off in accordance with a current supplied.

3. A circuit according to

claim 1

, wherein the fuse is comprised of an antifuse whose current path is short-circuited in accordance with a current supplied.

4. A circuit according to

claim 1

, wherein the control circuit has said output terminal put in a high impedance state after turning the thyristor ON.

5. A circuit according to

claim 4

, wherein the control circuit includes:

a decode section for decoding an address signal;

a signal generation circuit having an input terminal connected to the decode section and first and second output terminals, the signal generation circuit generating a first signal in accordance with an output signal of the decode section and a second signal delayed behind the first signal by a predetermined time and outputting the first signal from said first output terminal and the second signal from said second output terminal; and

a tri-state buffer having a first input terminal connected to said first output terminal of the signal generation circuit, a second input terminal connected to said second output terminal and a third output terminal connected to the gate electrode of the thyristor, the tri-state buffer outputting a potential for turning the thyristor ON from said third output terminal in accordance with said first signal supplied to said first input terminal and having said third output terminal put in a high impedance state in accordance with said second signal supplied to said second input terminal.

6. A circuit according to

claim 1

, wherein a potential of the control signal outputted from the control circuit is lower than a potential of the first power supply when the fuse is programmed.

7. A circuit according to

claim 1

, wherein the thyristor comprising:

a substrate of a first conductivity type;

a first well area of a second conductivity type formed in the substrate;

a second well area of the first conductivity type formed in the substrate;

a first gate area of the second conductivity type formed in the first well area;

an anode area of the first conductivity type formed in the first well area;

a second gate area of the first conductivity type formed in the second well area; and

a cathode area of the second conductivity type formed in the second well area.

8. A circuit according to

claim 1

, wherein the thyristor comprising:

a substrate of a first conductivity type;

a first well area of a second conductivity type formed in the substrate;

a second well area of the first conductivity type formed in the first well area;

a first gate area of the second conductivity type formed in the first well area;

an anode area of the first conductivity type formed in the first well area;

a second gate area of the first conductivity type formed in the second well area; and

a cathode area of the second conductivity type formed in the second well area.

9. A fuse programming circuit comprising:

a plurality of fuses having first and second ends and programmed in accordance with a current supplied, the first end of each of the fuses being connected to a first power supply;

a plurality of thyristors having first and second electrodes and first and second gate electrodes, the first electrode of the respective thyristor being connected to the second end of the corresponding fuse and the respective second electrode being connected to a second power lower in potential than the first power supply; and

a control circuit having an input terminal supplied with an input signal and a plurality of output terminals connected to the first and second gate electrodes of the respective thyristors, the control circuit generating a control signal for selecting one of the thyristors in accordance with the input signal.

10. A circuit according to

claim 9

, wherein the fuse is comprised of a fuse whose current path is cut off in accordance with a current supplied.

11. A circuit according to

claim 9

, wherein the fuse is comprised of an antifuse whose current path is short-circuited in accordance with a current supplied.

12. A circuit according to

claim 9

, wherein the control circuit has its output terminal put in a high impedance state after the thyristor is turned ON.

13. A circuit according to

claim 12

, wherein the control circuit includes:

a decode section for decoding an address signal;

a signal generation circuit having an input terminal connected to the decode section and first and second output terminals, the signal generation circuit generating a first signal in accordance with an output signal of the decode section and a second signal delayed behind the first signal by a predetermined time and outputting the first signal from said first output terminal and the second signal from said second output terminal; and

a tri-state buffer having a first input terminal connected to said first output terminal of the signal generation circuit, a second input terminal connected to said second output terminal and a third output terminal connected to the gate electrode of the thyristor, the tri-state buffer outputting a potential for turning the thyristor ON from said third output terminal in accordance with said first signal supplied to said first input terminal and having said third output terminal put in a high impedance state in accordance with said second signal supplied to said second input terminal.

14. A circuit according to

claim 9

, wherein the input signal is an address signal and the control circuit is comprised of a decoding circuit for decoding the address signal.

15. A circuit according to

claim 9

, wherein the control signals outputted from the control circuit at a time of programming the fuses are such that a first control signal supplied to the first gate electrode of the thyristor is set to be lower in potential than the first power supply and that a second control signal supplied to the second gate electrode of the thyristor is set to be higher in potential than the second power supply.

16. A circuit according to

claim 15

, wherein the thyristor comprising:

a substrate of a first conductivity type;

a first well area of a second conductivity type formed in the substrate;

a second well area of the first conductivity type formed in the substrate;

a first gate area of the second conductivity type formed in the first well area;

an anode area of the first conductivity type formed in the first well area;

a second gate area of the first conductivity type formed in the second well area; and

a cathode area of the second conductivity type formed in the second well area.

17. A circuit according to

claim 15

, wherein the thyristor comprising:

a substrate of a first conductivity type;

a first well area of a second conductivity type formed in the substrate;

a second well area of the first conductivity type formed in the first well area;

a first gate area of the second conductivity type formed in the first well area;

an anode area of the first conductivity type formed in the first well area;

a second gate area of the first conductivity type formed in the second well area; and

a cathode area of the second conductivity type formed in the second well area.

18. A fuse programming circuit comprising:

a plurality of antifuses having first and second ends and programmed by short-circuiting their current paths, the first end of the respective antifuse being connected to a first power supply;

a plurality of thyristors, each, connected to the second end of the corresponding antifuse, the respective thyristor supplying a voltage to the antifuse to allow the antifuse to be programmed; and

a decoder for selecting one of these thyristors in accordance with an address signal and turning that thyristor ON.

19. A circuit according to

claim 18

, wherein, after turning the thyristor ON, the decoder eliminates a minority carrier from the gate of the thyristor to turn the thyristor OFF.

20. A circuit according to

claim 18

, further comprising a first switch connected between the first ends of the respective antifuses and the first power supply, the first switch being turned ON when the selected antifuse is programmed and turned OFF after the antifuse has been programmed.

21. A circuit according to

claim 18

, further comprising a second switch connected between second electrodes of the respective thyristors and the second power supply, the second switch being turned ON when the selected antifuse is programmed and turned OFF after the antifuse has been programmed.

22. A circuit according to

claim 18

, wherein the thyristor has first and second gate electrodes and those control signals outputted from the control circuit at a time of programming the fuses are such that a first control signal supplied to the first gate electrode of the thyristor is set to be lower in potential than the first power supply and that a second control signal supplied to the second gate electrode of the thyristor is set to be higher in potential than the second power supply.

23. A circuit according to

claim 18

, wherein the input signal is the address signal and the control circuit is comprised of a decode circuit for decoding the address signal.

24. A circuit according to

claim 22

, wherein the thyristor comprising:

a substrate of a first conductivity type;

a first well area of a second conductivity type formed in the substrate;

a second well area of the first conductivity type formed in the substrate;

a first gate area of the second conductivity type formed in the first well area;

an anode area of the first conductivity type formed in the first well area;

a second gate area of the first conductivity type formed in the second well area; and

a cathode area of the second conductivity type formed in the second well area.

25. A circuit according to

claim 22

, wherein the thyristor comprising:

a substrate of a first conductivity type;

a first well area of a second conductivity type formed in the substrate;

a second well area of the first conductivity type formed in the first well area;

a first gate area of the second conductivity type formed in the first well area;

an anode area of the first conductivity type formed in the first well area;

a second gate area of the first conductivity type formed in the second well area; and

a cathode area of the second conductivity type formed in the second well area.

26. A phase programming circuit comprising:

a fuse programmed by being supplied with a current;

a thyristor having a current path and gate electrode, one end of the current path of the thyristor being connected to the fuse; and

a control circuit connected to the gate electrode of the thyristor, the control circuit turning the thyristor ON to allow the fuse to be programmed.