CHIP-ON-CHIP TESTING USING BIST

• US 20010050573A1
• Filed: 04/07/1999
• Published: 12/13/2001
• Est. Priority Date: 04/07/1999
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: DUMBRI, AUSTIN C.
• Granted Patent: US 6,456,101 B2
• Time in Patent Office: Days
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/3187 Built-in tests
• CPC Class Codes: G11C 2029/1206 Location of test circuitry on chip or wafer
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: H01L 2224/16145 the bodies being stacked

Abstract

An improved testable semi-conductor device is disclosed. An auxiliary BIST circuit is constructed in a primary chip to which a secondary chip is attached, thereby allowing testing of the secondary chip using the auxiliary BIST circuit. This allows direct test access to the secondary chip without the need for a separate BIST circuit to be included in the secondary IC chip and without using a primary BIST circuit of the primary IC chip to test the secondary chip.

Claims

1. An integrated circuit having a primary IC chip and a secondary IC chip electrically connected to each other, said primary IC comprising:

an auxiliary built-in-self-test (BIST) circuit for testing said secondary IC.

2. An integrated circuit as set forth in

claim 1

, wherein said primary IC further comprises:

a primary BIST circuit for testing portions of said primary IC.

3. An integrated circuit as set forth in

claim 1

, wherein said primary IC chip is an ASIC.

4. An integrated circuit as set forth in

claim 1

, wherein said primary IC chip is a digital signal processor (DSP).

5. An integrated circuit as set forth in

claim 1

, wherein said secondary IC chip is a memory chip.

6. An integrated circuit as set forth in

claim 1

, wherein said secondary IC chip is a DRAM.

7. An integrated circuit as set forth in

claim 1

, wherein said secondary IC chip is an SRAM.

8. An integrated circuit as set forth in

claim 1

, wherein said secondary IC chip is a nonvolatile memory.

9. An integrated circuit as set forth in

claim 8

, wherein said nonvolatile memory comprises a FLASH memory.

10. An integrated circuit as set forth in

claim 1

, wherein said primary IC chip and said secondary IC chip are physically connected in a chip-on-chip configuration.

11. A method of testing a secondary IC chip electrically connected to a primary IC chip, comprising the steps of:

providing said primary IC chip with an auxiliary built-in-self-test (BIST) circuit; and

testing said secondary IC chip using said auxiliary BIST circuit.

12. An auxiliary built-in-self -test (BIST) circuit in a primary integrated circuit (IC) chip, adapted to test a secondary IC chip.

13. An auxiliary BIST circuit as set forth in

claim 12

, wherein said primary and secondary IC'"'"'s are coupled in a chip-on-chip configuration.