Semiconductor memory device and control method
First Claim
1. A semiconductor memory device, comprising:
- a memory cell array having a plurality of word lines;
a word selection circuit that activates one of the plurality of word lines based on the value of an address;
a boosted potential coupled to the word selection circuit, the boosted potential providing charge to the activated word line; and
a boosted potential generation circuit coupled to provide the boosted potential, the boosted potential generation circuit providing charge to the boosted potential when the word line is to be activated.
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Accused Products
Abstract
A semiconductor memory device (50) having a boosted potential generation circuit is provided. The boosted potential generation circuit may provide charge to a boosted potential node when a word line (11) is to be activated. The boosted potential generation circuit may include a boosting control circuit (5), a boosted potential detection circuit (6), an oscillator circuit (7), and a booster circuit (8). The boosting control circuit (5) may generate a boosting control signal when a command decoder (1) indicates that a word line may be activated. In response to the boosting control signal, the boosted potential detection circuit (6) may enable the oscillator circuit (7) so that booster circuit (8) may transfer charge to the boosted potential node. This may allow the boosted potential node to have adequate charge that may be provided to the word line when activated.
6 Citations
20 Claims
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1. A semiconductor memory device, comprising:
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a memory cell array having a plurality of word lines;
a word selection circuit that activates one of the plurality of word lines based on the value of an address;
a boosted potential coupled to the word selection circuit, the boosted potential providing charge to the activated word line; and
a boosted potential generation circuit coupled to provide the boosted potential, the boosted potential generation circuit providing charge to the boosted potential when the word line is to be activated. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A control method for controlling a semiconductor memory device having a booster circuit that generates a boosted potential in response to an oscillation signal generated by an oscillator circuit, the method comprising the steps of:
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receiving a command and an address;
decoding the command;
generating a boosting control signal in response to the decoded command indicating that a word line is to be activated;
providing charge to a boosted potential node in response to the boosting control signal; and
providing an electrical connection between the boosted potential node and the word line in accordance with the value of the address received. - View Dependent Claims (10, 11, 12, 13)
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14. A semiconductor memory device, comprising:
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a memory cell array having a plurality of word lines;
a word selection circuit that activates one of the plurality of word lines based on an address value;
a boosting control circuit coupled to generate a boosting control signal in response to a control signal indicating that a word line is to be activated;
a boosted potential detection circuit coupled to receive the boosting control signal and provide a boosted voltage signal having an oscillator enable state and an oscillator disable state;
a boosted potential node coupled to the word selection circuit, the boosted potential node providing charge to the activated word line;
an oscillation circuit coupled to generate an oscillation signal that has periodic logic transitions when the boosted voltage signal is in the oscillator enable state; and
a booster circuit coupled to provide charge to the boosted potential node in response to logic transitions in the oscillation signal. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification