APPARATUS AND METHOD FOR PARTITIONED MEMORY PROTECTION IN CACHE COHERENT SYMMETRIC MULTIPROCESSOR SYSTEMS
First Claim
1. A method for partitioning memory in cache coherent symmetric multiprocessor system comprising of plurality of processors;
- a shared memory;
a shared communications bus; and
a memory controller, said method comprising the following steps;
subdividing said shared memory into independent regions and assigning each said region to one of said processors;
executing said processors in a single cache coherence domain on said shared communications bus;
intercepting and processing all memory access messages to detect if an address is outside of a memory region assigned to a processor in use; and
aborting an executed memory access operation and resetting said processor when an address violation of one of said memory region has been detected.
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Abstract
The present invention provides fault contained memory partitioning in a cache coherent, symmetric shared memory multiprocessor system while enabling fault contained cache coherence domains as well as cache coherent inter partition memory regions. The entire system may be executed as a single coherence domain regardless of partitioning, and the general memory access and cache coherency traffic are distinguished. All memory access is intercepted and processed by the memory controller. Before data is read from or written to memory, the address is verified and the executed operation is aborted if the address is outside the memory regions assigned to the processor in use. Inter cache requests are allowed to pass, though concurrently the accessed memory address is verified in the same manner as the memory requests. During the corresponding inter cache response, a failed validity check for the request results in the stopping of the requesting processor and the repair of the potentially corrupted memory hierarchy of the responding processor.
57 Citations
34 Claims
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1. A method for partitioning memory in cache coherent symmetric multiprocessor system comprising of plurality of processors;
- a shared memory;
a shared communications bus; and
a memory controller, said method comprising the following steps;
subdividing said shared memory into independent regions and assigning each said region to one of said processors;
executing said processors in a single cache coherence domain on said shared communications bus;
intercepting and processing all memory access messages to detect if an address is outside of a memory region assigned to a processor in use; and
aborting an executed memory access operation and resetting said processor when an address violation of one of said memory region has been detected. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- a shared memory;
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11. A computer program device readable by a machine, tangibly embodying a program of instructions executable by a machine to perform method steps for partitioning memory in cache coherent symmetric multiprocessor system comprising of plurality of processors;
- a shared memory;
a shared communications bus; and
a memory controller, said method comprising the following steps;
subdividing said shared memory into independent regions and assigning each said region to one of said processors;
executing said processors in a single cache coherence domain on said shared communications bus;
intercepting and processing all memory access messages to detect if an address is outside of a memory region assigned to a processor in use; and
aborting an executed memory access operation and resetting said processor when an address violation of one of said memory region has been detected. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
- a shared memory;
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21. An apparatus for partitioning memory in cache coherent symmetric multiprocessor system comprising of plurality of processors;
- a shared memory;
a shared communications bus; and
a memory controller, wherein said processors are executed in a single cache coherence domain, said apparatus comprising;
a means for subdividing said shared memory into independent regions and assigning each said region to one of said processors;
a partition management means to detect transactions attempting to access memory outside of a memory region assigned to a processor in use and processing said detected transactions to mark them as invalid; and
a transaction management means for aborting an executed memory access operation and resetting said processor in use when an address violation has been detected. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
- a shared memory;
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31. An apparatus for controlling partitioned memory in a cache coherent symmetric multiprocessor system comprising a shared memory;
- a shared communications bus;
a data queue; and
a memory controller, said apparatus comprising;
a transaction manager means for detecting memory address violations by transactions transmitted on said communications bus, and for marking said transactions as invalid if memory address violation is detected;
a capture buffer means to catch data being transmitted on said communications bus for each of said transactions; and
a multiplexer to steer data to be written to said memory from said capture buffer instead of said data queue according to a signal from said transaction manager. - View Dependent Claims (32, 33, 34)
- a shared communications bus;
Specification