APPARATUS AND METHOD FOR PARTITIONED MEMORY PROTECTION IN CACHE COHERENT SYMMETRIC MULTIPROCESSOR SYSTEMS

• US 20010052054A1
• Filed: 03/29/1999
• Published: 12/13/2001
• Est. Priority Date: 03/29/1999
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: FRANKE, HUBERTUS, JOSEPH, DOUGLAS J.
• Granted Patent: US 6,449,699 B2
• Time in Patent Office: Days
• US Class Current: 711/147
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/1458 by checking the subject access rights

Abstract

The present invention provides fault contained memory partitioning in a cache coherent, symmetric shared memory multiprocessor system while enabling fault contained cache coherence domains as well as cache coherent inter partition memory regions. The entire system may be executed as a single coherence domain regardless of partitioning, and the general memory access and cache coherency traffic are distinguished. All memory access is intercepted and processed by the memory controller. Before data is read from or written to memory, the address is verified and the executed operation is aborted if the address is outside the memory regions assigned to the processor in use. Inter cache requests are allowed to pass, though concurrently the accessed memory address is verified in the same manner as the memory requests. During the corresponding inter cache response, a failed validity check for the request results in the stopping of the requesting processor and the repair of the potentially corrupted memory hierarchy of the responding processor.

Claims

1. A method for partitioning memory in cache coherent symmetric multiprocessor system comprising of plurality of processors;

a shared memory;

a shared communications bus; and

a memory controller, said method comprising the following steps;

subdividing said shared memory into independent regions and assigning each said region to one of said processors;

executing said processors in a single cache coherence domain on said shared communications bus;

intercepting and processing all memory access messages to detect if an address is outside of a memory region assigned to a processor in use; and

aborting an executed memory access operation and resetting said processor when an address violation of one of said memory region has been detected.

2. The method of

claim 1

, wherein each of said processors has associated cache memory.

3. The method of

claim 2

, wherein said shared memory is accessible by each of said processors via said shared communications bus.

4. The method of

claim 3

, wherein said memory access traffic is processed by said memory controller.

5. The method of

claim 4

, wherein said memory controller provides partition address maps for specifying valid address ranges of said memory that each of said processors is allowed to access.

6. The method of

claim 5

, further establishing cache coherent inter partition shared memory regions for implementing shared locks and other inter-partition communication protocols by allowing overlaps in said partition address maps.

7. The method of

claim 6

, wherein said memory controller verifies the validity of each memory access executed by each of said processors against said partition address maps before accessing said memory.

8. The method of

claim 7

, wherein a cache coherence traffic is monitored without introducing additional cycles on said shared communications bus.

9. The method of

claim 8

, wherein each inter cache transaction is monitored and validated against said partition address maps.

10. The method of

claim 9

, wherein a copy of data associated with said inter cache transaction is kept and if a cache inconsistency results from said inter cache transaction said kept data is used to correct said cache inconsistency.

11. A computer program device readable by a machine, tangibly embodying a program of instructions executable by a machine to perform method steps for partitioning memory in cache coherent symmetric multiprocessor system comprising of plurality of processors;

a shared memory;

a shared communications bus; and

a memory controller, said method comprising the following steps;

subdividing said shared memory into independent regions and assigning each said region to one of said processors;

executing said processors in a single cache coherence domain on said shared communications bus;

intercepting and processing all memory access messages to detect if an address is outside of a memory region assigned to a processor in use; and

aborting an executed memory access operation and resetting said processor when an address violation of one of said memory region has been detected.

12. The computer program device of

claim 11

, wherein each of said processors has associated cache memory;

13. The computer program device of

claim 12

, wherein said shared memory is accessible by each of said processors via said shared communications bus.

14. The computer program device of

claim 13

, wherein said memory access traffic is processed by said memory controller.

15. The computer program device of

claim 14

, wherein said memory controller provides partition address maps for specifying valid address ranges of said memory that each of said processors is allowed to access.

16. The computer program device of

claim 15

, further establishing cache coherent inter partition shared memory regions for implementing shared locks and other inter-partition communication protocols by allowing overlaps in said partition address maps.

17. The computer program device of

claim 16

, wherein said memory controller verifies the validity of each memory access executed by each of said processors against said partition address maps before accessing said memory.

18. The computer program device of

claim 17

, wherein a cache coherence traffic is monitored without introducing additional cycles on said shared communications bus.

19. The computer program device of

claim 18

, wherein each inter cache transaction is monitored and validated against said partition address maps.

20. The computer program device of

claim 19

, wherein a copy of data associated with said inter cache transaction is kept and if a cache inconsistency results from said inter cache transaction said kept data is used to correct said cache inconsistency.

21. An apparatus for partitioning memory in cache coherent symmetric multiprocessor system comprising of plurality of processors;

a shared memory;

a shared communications bus; and

a memory controller, wherein said processors are executed in a single cache coherence domain, said apparatus comprising;

a means for subdividing said shared memory into independent regions and assigning each said region to one of said processors;

a partition management means to detect transactions attempting to access memory outside of a memory region assigned to a processor in use and processing said detected transactions to mark them as invalid; and

a transaction management means for aborting an executed memory access operation and resetting said processor in use when an address violation has been detected.

22. The apparatus of

claim 21

, wherein each of said processors has associated cache memory.

23. The apparatus of

claim 22

, wherein said shared memory is accessible by each of said processors via said shared communications bus.

24. The apparatus of

claim 23

, wherein said memory access traffic is processed by said memory controller.

25. The apparatus of

claim 24

, wherein said memory controller provides partition address maps for specifying valid address ranges of said memory that each of said processors is allowed to access.

26. The apparatus of

claim 25

, further establishing cache coherent inter partition shared memory regions for implementing shared locks and other inter-partition communication protocols by allowing overlaps in said partition address maps.

27. The apparatus of

claim 26

, wherein said memory controller verifies the validity of each memory access executed by each of said processors against said partition address maps before accessing said memory.

28. The apparatus of

claim 27

, wherein a cache coherence traffic is monitored without introducing additional cycles on said shared communications bus.

29. The apparatus of

claim 28

, wherein each inter cache transaction is monitored and validated against said partition address maps.

30. The apparatus of

claim 29

, wherein a copy of data associated with said inter cache transaction is kept and if memory inconsistency results from said inter cache transaction, said kept data is used to correct said cache inconsistency.

31. An apparatus for controlling partitioned memory in a cache coherent symmetric multiprocessor system comprising a shared memory;

a shared communications bus;

a data queue; and

a memory controller, said apparatus comprising;

a transaction manager means for detecting memory address violations by transactions transmitted on said communications bus, and for marking said transactions as invalid if memory address violation is detected;

a capture buffer means to catch data being transmitted on said communications bus for each of said transactions; and

a multiplexer to steer data to be written to said memory from said capture buffer instead of said data queue according to a signal from said transaction manager.

32. The apparatus of

claim 31

, wherein said transaction manager means aborts said transactions and resets said processor in use if said memory address violation is detected.

33. The apparatus of

claim 32

, further comprising a partition manager means to detect attempts by said transactions to access memory outside of a memory region assigned to said processor in use and to send a signal to said transaction manager means to mark said transaction as invalid.

34. The apparatus of

claim 33

, wherein said partition manager means accepts a transaction type, a memory address, and a cpu id of said processor in use signals for pending transactions from said communications bus.