BUFFERING SYSTEM BUS FOR EXTERNAL-MEMORY ACCESS
First Claim
1. A computer system comprising:
- memory;
a processor that issues data-transfer requests directed to said memory; and
a transfer path for conveying data-transfer requests including write requests between said processor and said memory, said transfer path including a system bus, and a system-bus buffer disposed between said system bus and said memory, said system-bus buffer being coupled to said system bus for storing said data-transfer requests, said system-bus buffer being coupled to said memory for providing said data-transfer requests thereto.
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Accused Products
Abstract
A computer system includes a processor, a cache, a system bus, a memory-control subsystem, an external memory bus, RAM memory, and flash memory. All but the last three are fabricated on a single ASIC. The memory control subsystem includes a RAM controller, a flash-memory controller, and a memory interface between the controllers and the memories. In addition, the memory-control subsystem includes a system-bus FIFO write buffer. During an external-memory access, the request information is transferred from the system bus to the system-bus buffer instead of directly to the memory interface. The system-bus buffer stores address data, content data (in the case of a write request), and control data. In turn, the control data is forwarded to the appropriate controller and the address data and the content data are forwarded to external memory bus. Note that only one system-bus write buffer is required despite the plural memory controllers. While the processor write buffer frees the processor for other tasks while a write operation is being completed, the system-bus write buffer frees the system bus for other tasks while a write operation is being completed. The system-bus buffer thus allows other operations to utilize the system bus during an external-memory access.
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Citations
8 Claims
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1. A computer system comprising:
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memory;
a processor that issues data-transfer requests directed to said memory; and
a transfer path for conveying data-transfer requests including write requests between said processor and said memory, said transfer path including a system bus, and a system-bus buffer disposed between said system bus and said memory, said system-bus buffer being coupled to said system bus for storing said data-transfer requests, said system-bus buffer being coupled to said memory for providing said data-transfer requests thereto. - View Dependent Claims (2, 3, 4, 5)
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6. A method for executing a write request, said method comprising the steps of:
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issuing said write request from a processor;
transferring said write request to a system-bus buffer via a system bus, and transferring said write request from said system-bus buffer to a main memory. - View Dependent Claims (7, 8)
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Specification