EFFICIENT SAVING AND RESTORING STATE IN TASK SWITCHING

• US 20010052065A1
• Filed: 03/31/1998
• Published: 12/13/2001
• Est. Priority Date: 03/31/1998
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: FISCHER, STEPHEN A., BIGBEE, BRYANT E., THAKKAR, SHREEKANT S., ROUSSEL, PATRICE L., HUFF, THOMAS, ALEXANDER, WILLIAM C. III
• Granted Patent: US 6,898,700 B2
• Time in Patent Office: Days
• US Class Current: 712/228
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/462 with multiple register sets

Abstract

The present invention discloses a method and apparatus for saving and restoring registers. A single instruction is decoded. The single instruction moves contents of a plurality of registers associated with a functional unit in a processor to a memory; the processor operates under a plurality of operational modes and operand sizes. The single instruction arranges the contents in the memory according to a predetermined format into a plurality of groups, each group is aligned at an address boundary which corresponds to a multiple of 2^N bytes. The predetermined format is constant for the plurality of operational modes and operand sizes. The single instruction retains the contents of the plurality of registers after moving.

Claims

1. A method comprising:

decoding a single instruction by a processor, said processor operating under a plurality of operational modes and operand sizes;

in response to said decoding said single instruction

moving contents of a plurality of registers associated with at least a functional unit in the processor to a memory;

arranging the contents in the memory according to a predetermined format into a plurality of groups, each group being aligned at an address boundary which corresponds to a multiple of 2^N bytes, the predetermined format being constant for the plurality of operational modes and operand sizes; and

retaining the contents of the plurality of registers after moving.

2. The method of

claim 1

wherein said functional unit is one of a floating-point unit (FPU), a packed data unit, and an extended packed data unit.

3. The method of

claim 2

wherein said plurality of registers include an FPU control word, an FPU status word, an FPU tag word, an FPU opcode, an instruction pointer, a code segment, a data pointer, a data segment, a packed data control and status word, an aliased set of floating-point and packed data registers, and a set of extended packed data registers.

4. The method of

claim 1

wherein said plurality of operational modes include a protected mode and a real-address mode.

5. The method of

claim 1

wherein said plurality of operand sizes include 16-bit and 32-bit.

6. The method of

claim 3

wherein said moving moves a plurality of valid bits in the FPU tag word, each of the valid bits corresponding to each of the registers associated with the FPU.

7. The method of

claim 1

wherein N is a positive integer number.

8. A method comprising decoding a single instruction by a processor, said processor operating under a plurality of operational modes and operand sizes;

and

in response to said decoding said single instruction

accessing a plurality of groups arranged in a predetermined format in a memory, each group being aligned at an address boundary which corresponds to a multiple of 2^N bytes, the predetermined format being constant for the plurality of operational modes and operand sizes, and

moving contents of the plurality of groups to a plurality of registers associated with at least a functional unit in the processor.

9. The method of

claim 8

wherein said functional unit is one of floating-point unit (FPU), a packed data unit, and an extended packed data unit.

10. The method of

claim 9

wherein said plurality of registers include an FPU control word, an FPU status word, an FPU tag word, an FPU opcode, an instruction pointer, a code segment, a data pointer, a data segment, a packed data control and status word, an aliased set of floating-point and packed data registers, and a set of extended packed data registers.

11. The method of

claim 8

wherein said plurality of operational modes include a protected mode and a real-address mode.

12. The method of

claim 8

wherein said plurality of operand sizes include 16-bit and 32-bit.

13. The method of

claim 9

wherein said moving moves a plurality of valid bits in the FPU tag word, each of the valid bits corresponding to each of the registers associated with the FPU.

14. The method of

claim 8

wherein N is a positive integer number.

15. An apparatus for use in a computer system comprising:

a processor having at least a functional unit, said processor operating under a plurality of operational modes and operand sizes;

a plurality of registers associated with the functional unit; and

a memory coupled to the processor for storing contents of the plurality of registers according to a predetermined format into a plurality of groups, each group being aligned at an address boundary which corresponds to a multiple of 2^N bytes, the predetermined format being constant for the plurality of operational modes and operand sizes.

16. The apparatus of

claim 15

wherein the functional unit is one of a floating-point unit (FPU), a packed data unit, and an extended packed data unit.

17. The apparatus of

claim 16

wherein said plurality of registers include an FPU control word, an FPU status word, an FPU tag word, an FPU opcode, an instruction pointer, a code segment, a data pointer, a data segment, a packed data control and status word, an aliased set of floating-point and packed data registers, and a set of extended packed data registers.

18. The apparatus of

claim 15

wherein said plurality of operational modes include a protected mode and a real-address mode.

19. The apparatus of

claim 15

wherein said plurality of operand sizes include 16-bit and 32-bit.

20. The apparatus of

claim 15

wherein N is a positive integer number.