Memory testing method and memory testing apparatus

• US 20010052093A1
• Filed: 04/27/2001
• Published: 12/13/2001
• Est. Priority Date: 05/02/2000
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Japan Aviation Electronics Industry Limited
• Inventors: Oshima, Hiromi, Kawata, Yasuhiro, Okino, Noboru
• Granted Patent: US 6,877,118 B2
• Time in Patent Office: Days
• US Class Current: 714/719
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A memory testing method and apparatus are provided, which can test in short time a flash memory. In case of testing a flash memory having block function, in a memory testing method and apparatus in which a predetermined logical value is written in memory cells constituting each of blocks of the memory, the written logical value is read out from the memory cells to compare it with an expected value, and a decision that, when the read-out logical value and the expected value do not coincide with each other, such memory cell is a failure memory cell, a decision is rendered that, when the number of failure memory cells in each block reaches a predetermined number, such block is a bad block, and the test of such block is stopped. In addition, a decision is rendered that, when the number of failure memory cells on the same address line reaches a predetermined number, such address line is a bad address line, and after such decision has rendered, the test of memory cells on the bad address line is substantially not effected.

Claims

1. A memory testing method comprising the steps of:

writing a predetermined logical value in memory cells constituting each of blocks of a memory having block function;

reading out the written logical value from the memory cells in each block;

rendering a decision that, when the written logical value and the read-out logical value do not coincide with each other, such memory cell is a failure memory cell; and

discontinuing, when the number of failure memory cells in a block being now tested reaches a predetermined number, the test of such block.

2. The method as set forth in

claim 1

, further comprising the step of transferring, at the time point that the test of such block has been discontinued, a block to be tested to the next block.

3. The method as set forth in

claim 1

, further comprising the step of rendering a decision that, when the number of failure memory cells in a block being now tested reaches a predetermined number, such block is to be repaired by a spare block, and

wherein when such repair decision is rendered, the test of such block is discontinued.

4. The method as set forth in

claim 1

, wherein in case a plurality of memories are concurrently tested, when a decision is rendered that a block of a memory being now tested is to be repaired by a spare block, the test of such block of the memory is interrupted, and the test of the next block of the memory is started in synchronism with the transfer of the test of the remaining memory or memories to the next block thereof.

6. The memory testing method as set forth in any one of

claims 1

to

5

, wherein when the number of blocks each being decided to be repaired by a spare block exceeds a predetermined allowable value, the memory being now tested is ended in test to be conducted thereafter.

5. A memory testing method comprising the steps of:

writing a predetermined logical value in memory cells constituting each of blocks of a memory having block function;

reading out the written logical value from the memory cells in each block;

rendering a decision that, when the written logical value and the read-out logical value do not coincide with each other, such memory cell is a failure memory cell; and

masking, when the number of failure memory cells on the same address line reaches a predetermined number, the test of memory cells on said address line in other block or blocks to be tested thereafter.

7. A memory testing apparatus for testing whether or not a predetermined logical value is correctly written in memory cells constituting each of blocks of a memory having block function, said memory testing apparatus comprising:

bad block detection and storage means detecting the presence of a failure memory cell in each block, rendering a decision that, when the number of failure memory cells in each block reaches a predetermined number, such block is a bad block, and storing therein the result of the decision;

bad address line detection and storage means detecting the presence of a failure memory cell on the same address line, rendering a decision that, when the number of failure memory cells on the address line reaches a predetermined number, said address line is a bad address line, and storing therein the result of the decision; and

mask control means controlling to interrupt, when said bad block detection and storage means has rendered a decision that a block being now tested is a bad block, the test of the block being now tested and to write, when said bad address line detection and storage means has detected a bad address line, a forced writing signal in memory cells on the detected bad address line in the test of other block or blocks to be tested thereafter, thereby to exclude such memory cells from memory cells to be tested.

8. The memory testing apparatus as set forth in

claim 7

, further comprising:

bad memory detecting means rendering a decision that, when it detects that a predetermined number of bad blocks has been stored in said bad block detection and storage means, the memory being tested from which such bad blocks have been generated is a bad memory; and

mask control means controlling to stop, after the time point that said bad memory detecting means has rendered a decision that the memory being tested is a bad memory, the test of the memory.