Memory system and programming method thereof

• US 20010053092A1
• Filed: 05/25/2001
• Published: 12/20/2001
• Est. Priority Date: 06/12/2000
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Okaue, Takumi, Kosaka, Hideo, Hashiguchi, Akihiko
• Granted Patent: US 6,426,895 B2
• Time in Patent Office: Days
• US Class Current: 365/185.19
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A memory system and its programming method capable of reducing programming time for each page versatility thereof is high, wherein the memory cell array is constituted, by a MONOS-type (MNOS-type) non-volatile memory or floating gate non-volatile memory in which a source side channel hot electron injection that enables the memory to write therein data by each divided unit (for instance, each 64 bytes=512 bits) is carried out, instead of the write operation where writing is carried out collectively by each page unit (512 bytes). Further, there is provided an emulation circuit successively storing programming data that constitutes the page of a plurality of divided units, and a control circuit successively reading the held divided unit data so as to write to the non-volatile memory.

Claims

1. A memory system in which a program is completed with a page as a unit, comprising:

an intermediate circuit successively holding program data that forms said page in a division unit where the program data are divided into a plurality of division units;

a memory cell array in which a plurality of memory cells each including at least one memory transistor having a control gate controlling a charge accumulating means and a charge quantity accumulated in said charge accumulating means, and at least one selection transistor having a shared channel formation region and said memory transistor are arranged, and in which the plurality of memory cells arranged in a direction of a word line are connected in a cascade connection;

word lines to which a gate of the selection transistor of each memory cell cascade-connected in the direction of said word line are commonly connected; and

a control circuit successively reading the divided unit data held in said intermediate circuit when programming, electrically dividing said memory cell array in every interval of a plurality of the memory cells in response to said division unit in the direction of the word line by driving the control gate of said memory transistor, and writing said division unit data to said memory cell array by parallel applying programming pulses to the control gates of the memory transistors in a predetermined bit unit.

2. A memory system according to

claim 1

, wherein said control circuit carries out an application of the programming pulse in parallel, and continuously carries out the verification in all the same bit unit.

3. A memory system according to

claim 1

, wherein the charge accumulating means of said memory cell comprises an insulating film including a nitride film.

4. A memory system according to

claim 1

, wherein said memory cell includes a first memory transistor, a second memory transistor and a selection transistor formed to have a common channel formation region between said first memory transistor and said second memory transistor, and the charge accumulating means of both said memory transistor and said second memory transistor is included in the insulating film including the nitride film, and

the first memory transistor of one memory cell and the second memory transistor of a memory cell adjacent to said one memory,cell commonly having an insulating film as the control gate and the charge accumulating means.

5. A memory system in which a program is completed with a page as a unit comprising:

a plurality of divided circuits each having

an intermediate circuit successively holding programming data that forms said page in a division unit where the program data is divided into a plurality of division units,

a memory cell array in which a plurality of memory cells including at least one memory transistor having a control gate controlling a charge accumulating means and a charge quantity accumulated in said charge accumulating means, and at least one selection transistor having a shared channel formation region and said memory transistor are arranged, and in which the plurality of memory cells arranged in the direction of a word line are connected in a cascade connection; and

word lines to which a gate of the selection transistor of each memory cell cascade-connected in the direction of said word line are connected commonly; and

a control circuit constituting pages in such a way as to range over a plurality of divided circuits, successively reading a divided unit data held in said intermediate circuit when programming, electrically dividing said memory cell array at intervals of a plurality of the memory cells corresponding to said divided unit in the direction of the word line by driving the control gate of said memory transistor of each divided circuit, and writing said divided unit data to said memory cell array by applying programming pulses in parallel to the control gate of the memory transistor in a predetermined bit unit with ranging over the plurality of divided circuits.

6. A memory system according to

claim 5

, wherein said control circuit carries out the programming pulse application in parallel, continuously carries out the verification in every the same bit unit.

7. A memory system according to

claim 5

, wherein the charge accumulating means of said memory cell comprises an insulating film including a nitride film.

8. A memory system according to

claim 5

, wherein said memory cell includes a first memory transistor, a second memory transistor and a selection transistor formed to have a common channel formation region between said first memory transistor and said second memory transistor, and said charge accumulating means of both said memory transistor and said second memory transistor is included in the insulating film including the nitride film, and

the first memory transistor of one memory cell and the second memory transistor of a memory cell adjacent to said one memory cell commonly having an insulation film as the control gate and the charge accumulating means.

9. A programming method for a memory system having a memory cell array in which a plurality of memory cells each including at least one memory transistor having a control gate controlling a charge accumulating means and a charge quantity accumulated in said charge accumulating means, and at least one selection transistor having a shared channel formation region and said memory transistor are arranged, and in which a plurality of memory cells arranged in a direction of a word line are connected in a cascade connection, and in which a programming is completed with a page as a unit, comprising the steps of:

successively holding programming data that forms a page in a division unit where the program data is divided into a plurality of division units;

successively reading the held divided unit data;

electrically dividing said memory cell array in every interval of a plurality of memory cells corresponding to said divided unit in the direction of the word line by driving the control gate of said memory transistor; and

successively writing said divided unit data to said memory cell array by carrying out parallel programming pulse application to the control gate of the memory transistor in a predetermined bit unit.

10. A programming method of the memory system according to

claim 9

, wherein writing of the divided unit data is executed in such a way as to carry out programming pulse application in parallel, and to carry out the verification of the same bit unit continuously.

11. A programming method for a memory system having a plurality of divided circuits each including a memory cell array in which a plurality of memory cells each including at least one memory transistor having a control gate controlling a charge accumulating means and a charge quantity accumulated in said charge accumulating means, and at least one selection transistor having a shared channel formation region and said memory transistor are arranged, and in which a plurality of memory cells arranged in the direction of a word line are connected in a cascade connection, in which a programming is completed with a page as a unit, comprising the steps of:

successively holding programming data that forms a page in a division unit, where the program data is divided into a plurality of division units;

forming said page in such a way as to range over a plurality of divided circuits;

successively reading the held divided unit data;

electrically dividing said memory cell array in every interval of a plurality of memory cells corresponding to said divided unit in the direction of the word line by driving the control gate of said memory transistor of each said divided circuit; and

successively writing said divided unit data to said memory cell array by carrying out parallel programming pulse application to the control gate of the memory transistor in a predetermined bit unit ranging over a plurality of divided circuits.

12. The programming method of the memory system according to

claim 11

, wherein writing of the divided unit data is executed in such a way as to carry out programming pulse application in parallel, and to carry out the verification of the same bit unit continuously.