Multistage digital cross connect with synchronized configuration switching

• US 20010053160A1
• Filed: 01/16/2001
• Published: 12/20/2001
• Est. Priority Date: 04/11/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Velio Communications, Inc. (Broadcom, Inc.)
• Inventors: Dally, William J.
• Granted Patent: US 7,301,941 B2
• Time in Patent Office: Days
• US Class Current: 370/535
• CPC Class Codes: H04J 2203/0003 Switching fabrics, e.g. transport network, control network
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections
• CPC Class Codes: H04Q 11/06 Time-space-time switching
• CPC Class Codes: H04Q 2213/1302 Relay switches
• CPC Class Codes: H04Q 2213/1304 Coordinate switches, crossbar, 4/2 with relays, coupling field
• CPC Class Codes: H04Q 2213/13076 Distributing frame, MDF, cross-connect switch
• CPC Class Codes: H04Q 2213/13103 Memory
• CPC Class Codes: H04Q 2213/13292 Time division multiplexing, TDM
• CPC Class Codes: H04Q 2213/13305 Transistors, semiconductors in general
• CPC Class Codes: H04Q 2213/1334 Configuration within the switch
• CPC Class Codes: H04Q 2213/13367 Hierarchical multiplexing, add-drop multiplexing
• CPC Class Codes: H04Q 2213/13393 Time slot switching, T-stage, time slot interchanging, TSI
• CPC Class Codes: H04Q 3/68 Grouping or interlacing selector groups or stages

Abstract

A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized data frame. Both the configuration data and a frame clock may be propagated through the plural stages from a master switch. First and last stages of the digital cross connect may be implemented on common chips having two framing time bases. Data may be aligned to a global frame clock and interchanged using a single random access memory in a time slot interchanger. The write address to the random access memory is generated from a local frame counter keyed to the input data frame while a read address is transformed from a global frame counter.

Claims

1. A digital cross connect comprising:

plural switching stages, each stage having plural switches receiving plural frames of time multiplexed input data and switching the data in time and space; and

configuration storage at each switch storing a time/space configuration for the switch, all switches switching configuration to the stored time/space configuration in frame synchronization at the start of synchronized data frames by synchronizing switches of successive stages to a configuration select signal propagated from at least one switch of an input stage.

2. A cross connect as claimed in

claim 1

wherein the configuration select signal is embedded within a frame of data.

3. A cross connect as claimed in

claim 2

wherein the configuration select signal is embedded in an A1 byte of a SONET frame.

4. A cross connect as claimed in

claim 3

wherein the configuration select signal is embedded in the fourth A1 byte of an STS-48 frame.

5. A cross connect as claimed in

claim 1

wherein configuration switching is initiated by a prepare-to-switch signal propagated from a master switch to all switches of an output stage and the input stage, the at least one switch of the input stage then propagating the configuration select signal.

6. A cross connect as claimed in

claim 5

wherein the prepare-to-switch signal is embedded within a frame of data.

7. A cross connect as claimed in

claim 6

wherein the prepare-to-switch signal is embedded in an A1 byte of a SONET frame.

8. A cross connect as claimed in

claim 7

wherein the prepare-to-switch signal is embedded in the second and third bytes of an STS-48 frame.

9. A cross connect as claimed in

claim 5

wherein switches of the first and last stages are on common chips.

10. A cross connect as claimed in

claim 9

wherein the common chips of the first and last stages support respective framing time bases for the first and last stages.

11. A cross connect as claimed in

claim 9

wherein connections from the first stage expand in space from input connections, and connections to the last stage concentrate in space to output connections.

12. A cross connect as claimed in

claim 11

wherein chips of a common design support the switches of all stages.

13. A cross connect as claimed in

claim 5

wherein the prepare-to-switch signal from the master switch is in a signal which is qualified to distinguish the signal from the master switch from signals from other switches.

14. A cross connect as claimed in

claim 13

wherein the qualifier and the configuration data are embedded in A1 bytes of a SONET frame.

15. A cross connect as claimed in

claim 5

wherein the master switch is in a middle stage.

16. A cross connect as claimed in

claim 1

wherein each switch comprises a time slot interchanger associated with each input and output port thereof and a space switch.

17. A method of cross connecting digital data comprising:

providing plural switching stages, each stage having plural switches receiving plural frames of time multiplexed input data and switching the data in time and in space;

providing configuration storage at each switch to store a time/space configuration for the switch;

propagating a configuration select signal from at least one input switch of an input stage to successive stages; and

switching configuration of the switches to the stored time/space configurations in frame synchronization at the start of synchronized data frames by synchronizing switches of the successive stages to the configuration select signal.

18. A method as claimed in

claim 17

wherein the configuration select signal is embedded within a frame of data.

19. A method as claimed in

claim 18

wherein the configuration select signal is embedded in an A1 byte of a SONET frame.

20. A method as claimed in

claim 19

wherein the configuration select signal is embedded in the fourth A1 byte of an STS-48 frame.

21. A method as claimed in

claim 17

wherein configuration switching is initiated by a prepare-to-switch signal propagated from a master switch to all switches of an output stage and the input stage, the at least one switch of the input stage then propagating the configuration select signal.

22. A method as claimed in

claim 21

wherein the prepare-to-switch signal is embedded within a frame of data.

23. A method as claimed in

claim 22

wherein the prepare-to-switch signal is embedded in an A1 byte of a SONET frame.

24. A method as claimed in

claim 23

wherein the prepare-to-switch signal is embedded in the second and third bytes of an STS-48 frame.

25. A method as claimed in

claim 21

wherein switches of the first and last stages are on common chips.

26. A method as claimed in

claim 25

further comprising switching the data of the first and last stages in synchronization with respective framing time bases for the first and last stages.

27. A method as claimed in

claim 25

wherein the frames from the first stage expand in space from input connections, and frames to the last stage concentrate in space to output connections.

28. A method as claimed in

claim 27

wherein chips of a common design support the switches of all stages.

29. A method as claimed in

claim 21

wherein the prepare-to-switch signal from the master switch is in a signal which is qualified to distinguish the master signal from signals from other switches.

30. A method as claimed in

claim 29

wherein the qualifier and the configuration data are embedded in A1 bytes of a SONET frame.

31. A method as claimed in

claim 21

wherein the master switch is in a middle stage.

32. A method as claimed in

claim 17

wherein each switch comprises a time slot interchanger associated with each input and output port thereof and a space switch.

33. A digital cross connect comprising:

plural switching stages, each stage having plural switching means for receiving plural frames of time multiplexed input data and switching the data in time and space;

configuration storage means at each switch for storing a time/space configuration for the switch; and

means for switching configuration of the switches to the stored time/space configuration in synchronization with a configuration select signal propagated from at least one input switching means of an input stage.

34. A digital cross connect comprising:

plural switching stages, each stage having plural switches, each comprising a time slot interchanger associated with each input and output port thereof and a space switch, each switch receiving plural frames of time multiplexed input data and switching the data in time and space; and

configuration storage at each switch storing a time/space configuration for the switch, all switches switching configuration to the stored time/space configuration in frame synchronization at the start of synchronized data frames.

35. A method of cross connecting digital data comprising:

providing plural switching stages, each stage having plural switches, each comprising a time slot interchanger associated with each input and output port thereof and a space switch, each switch receiving plural frames of time multiplexed input data and switching the data in time and in space;

providing configuration storage at each switch to store a time/space configuration for the switch; and

switching configuration of the switches to the stored time/space configurations in frame synchronization at the start of synchronized data frames by synchronizing switches of the successive stages to the configuration select signal.

36. A digital cross connect comprising:

plural switching stages, each stage having plural switching means, each comprising a time slot interchanger associated with each input and output port thereof and a space switch, for receiving plural frames of time multiplexed input data and switching the data in time and space;

configuration storage means at each switch for storing a time/space configuration for the switch; and

means for switching configuration of the switches to the stored time/space configuration in frame synchronization at the start of synchronized data frames.

37. A digital cross connect comprising plural switching stages, each stage having plural switches on plural chips receiving plural frames of time multiplexed input data and switching the data in time and space, switches of different stages being on common chips supporting respective framing time bases for the different stages.

38. A cross connect as claimed in

claim 37

wherein connections from a first stage expand in space from input connections and connections to a second stage concentrate in space to output connections.

39. A cross connect as claimed in

claim 37

wherein the different stages are first and final stages of the plural switching stages.

40. A cross connect as claimed in

claim 39

wherein connections from the first stage expand in space from input connections, and connections to the final stage concentrate in space to output connections.

41. A switch circuit on an integrated circuit chip comprising:

switch circuitry receiving plural frames of time multiplexed input data and switching the data in time and space;

a first frame counter to which a first portion of the plural frames of time multiplexed input data is synchronized; and

a second frame counter to which a second portion of the plural frames of time multiplexed input data is synchronized.

42. A switching circuit as claimed in

claim 41

wherein connections expand in space from input connections to the first portion, and connections concentrate in space to output connections of the second portion.

43. Switching circuitry as claimed in

claim 41

which responds to a prepare-to-switch signal received with the second portion to initiate a configuration select signal propagated with the first portion.

44. Switching circuitry as claimed in

claim 43

wherein the configuration select signal is embedded within a frame of data.

45. Switching circuitry as claimed in

claim 44

wherein the configuration select signal is embedded in an A1 byte of a SONET frame.

46. Switching circuitry as claimed in

claim 45

wherein the configuration select signal is embedded in the fourth A1 byte of an STS-48 frame.

47. Switching circuitry as claimed in

claim 44

wherein the prepare-to-switch signal is embedded within a frame of data.

48. Switching circuitry as claimed in

claim 47

wherein the configuration select signal and the prepare to switch signal are embedded within A1 bytes of a SONET frame.

49. Switching circuitry as claimed in

claim 43

wherein the prepare-to-switch signal is embedded within a frame of data.

50. Switching circuitry as claimed in

claim 49

wherein the prepare-to-switch signal is embedded in an A1 byte of a SONET frame.

51. Switching circuitry as claimed in

claim 50

wherein the prepare-to-switch signal is embedded in the second and third bytes of an STS-48 frame.

52. Switching circuitry as claimed in

claim 41

wherein input frames to and output frames from the switch circuitry are programmably assignable to the first and second portions.