Package substrate

• US 20010055203A1
• Filed: 07/17/2001
• Published: 12/27/2001
• Est. Priority Date: 10/17/1997
• Status: Active Grant

• Current Assignee: Ibiden Co., Ltd.
• Original Assignee: Ibiden Co., Ltd.
• Inventors: Asai, Motoo, Mori, Yoji
• Granted Patent: US 6,487,088 B2
• Time in Patent Office: Days
• US Class Current: 361/794
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15173 in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0271 Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 1/114 : Pad being close to via, but not surrounding the via
• CPC Class Codes: H05K 1/116 : Lands, clearance holes or other lay-out details concerning the surrounding of a via
• CPC Class Codes: H05K 2201/09472 : Recessed pad for surface mounting; Recessed electrode of component
• CPC Class Codes: H05K 2201/09509 : Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09627 : Special connections between adjacent vias, not for grounding vias
• CPC Class Codes: H05K 2201/09781 : Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/3457 : Solder materials or compositions; Methods of application thereof
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4644 : by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602

Abstract

According to the package board of the present invention, each soldering pad formed on the top surface of the package board, on which an IC chip is to be mounted, is small (133 to 170 μm in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also small. On the other hand, each soldering pad formed on the bottom surface of the package board, on which a mother board, etc. are to be mounted, is large (600 μm in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also large. Consequently, a dummy pattern 58M is formed between conductor circuits 58U and 58U for forming signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.

Claims

1. A package board having a core board on each surface of which a plurality of conductor circuits are formed with an interlaminar resin insulating layer therebetween, wherein a plurality of soldering pads are formed on the IC chip mounted side surface, as well as on the other side surface to be connected to another board, so that said soldering pads on the other side surface are larger than those on said IC chip side surface of said package board, and

a dummy pattern is formed between conductor circuit patterns formed on said IC chip mounted side surface of said core board.

2. A package board having a core board on each surface of which a plurality of conductor circuits are formed with an interlaminar resin insulating layer therebetween, wherein a plurality of soldering pads are formed on the IC chip side surface, as well as on the other side surface to be connected to another board, so that said soldering pads on the other side surface are larger than those on said IC chip side surface of said package board, and

a dummy pattern is formed at the outer periphery of each conductor circuit formed on said IC chip side of said core board.

3. A package board composed as a multi-layer wiring board, comprising:

a plurality of conductor circuits formed in an outermost layer;

an insulating layer for supporting a plurality of said conductor circuits formed in said outermost layer; and

a plurality of inner layer conductor circuits formed under said insulating layer, wherein

a plurality of said inner layer conductor circuits are a power supply layer and/or a ground layer,

a soldering bump is formed, through said insulating layer, on each via-hole connected to an inner layer conductor circuit.

4. A package board composed as a multi-layer printed wiring board, comprising:

first conductor circuit formed in an inner layer;

first interlaminar resin insulating layer formed on said first inner layer conductor circuit;

second inner layer conductor circuit formed on said first interlaminar resin insulating layer;

second interlaminar resin insulating layer formed on said second conductor circuit; and

a plurality of conductor circuits formed in the outermost layer formed on said second interlaminar resin insulating layer, wherein

a plurality of said second conductor circuits in said inner layer is a power supply layer and/or a ground layer, and

a soldering bump is formed, through said second interlaminar resin insulating layer, in each via-hole connected to a second conductor circuit.

5. A package board having a core board with a conductor layer formed on each surface, another conductor layer formed on said conductor layer with an interlaminar resin insulating layer therebetween, and a conductor layer on either of said surfaces of said core board being used as an electrode layer, wherein

the land of a through-hole of said core board, disposed in a conductor layer formed as said electrode layer, is united with a pad connected to a via-hole formed through an interlaminar resin insulating layer formed on the top surface of said package board.

6. A package board having a core board on each surface of which a conductor layer is formed, and another conductor layer is formed on said conductor layer with an interlaminar resin insulating layer therebetween, and a conductor layer formed on the top of any of said interlaminar resin insulating layers is used as an electrode layer, wherein

the land of a via-hole formed through an interlaminar resin insulating layer formed on the bottom surface of said package board, disposed in a conductor layer formed as said electrode layer, is united with a pad connected to a via-hole formed through an interlaminar resin insulating layer formed on the top surface of said package board.

7. A package board comprising a multi-layer conductor circuit formed with each of a plurality of interlaminar resin insulating layers therebetween, a plurality of soldering bumps formed on the IC chip mounted side surface, as well as on the other surface connected to another board so that a space between the surface connected to another board and another board is sealed with resin, wherein

a soldering bump formed on the surface of said package board, connected to another board, is formed in a via-hole.

8. A package board comprising a multi-layer conductor circuit formed with each of a plurality of interlaminar resin insulating layers therebetween, a plurality of soldering bumps formed both on the IC chip mounted side surface and on the other side surface connected to another board so that a space between said surface connected to another board and another board is sealed with resin, wherein

each of said soldering bumps formed on the surface of said package board, connected to another board, is formed on each of a plurality of via-holes.