Initiate flow control mechanism of a modular multiprocessor system

• US 20010055277A1
• Filed: 05/11/2001
• Published: 12/27/2001
• Est. Priority Date: 05/31/2000
• Status: Abandoned Application

• Current Assignee: Compaq Computer Corporation (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Steely, Simon C. Jr., Van Doren, Stephen R., Tierney, Gregory E., Sharma, Madhumitra
• Application Number:
  US09/853,301
• Publication Number:
  US 20010055277A1
• Time in Patent Office: Days
• US Class Current: 370/236
• CPC Class Codes: H04L 47/20 Traffic policing
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 47/29 using a combination of thresholds
• CPC Class Codes: H04L 47/52 by attributing bandwidth to queues
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/505 Corrective measures

Abstract

An initiate flow control mechanism prevents interconnect resources within a switch fabric of a modular multiprocessor system from being dominated with initiate transactions. The multiprocessor system comprises a plurality of nodes interconnected by a switch fabric that extends from a global input port of a node through a hierarchical switch to a global output port of the same or another node. The interconnect resources include shared buffers within the global ports and hierarchical switch. The initiate flow control mechanism manages these shared buffers to reserve bandwidth for complete transactions when extensive global initiate traffic to one or more nodes of the system may create a bottleneck in the switch fabric.

Claims

1. A method for performing flow control to prevent a shared buffer resource of a switch fabric within a modular multiprocessor system from being saturated with initiator transaction packets, the switch fabric interconnecting a plurality of nodes of the system and configured to transport initiator and responder transaction packets from a global output port of a first node through a hierarchical switch to a global input port of a second node, the method comprising the steps of:

providing one or more initiate counters at the hierarchical switch;

incrementing the initiate counter each time an initiator transaction packet is received at the shared buffer resource of the switch fabric;

if the initiate counter exceeds a predefined threshold, asserting an initiate flow control signal to each global output port of the multiprocessor system;

in response to assertion of the initiate flow control signal, stopping the global output ports of the multiprocessor system from issuing at least some initiator transaction packets, but permitting the global output ports to continue issuing responder transaction packets.

2. The method of

claim 1

wherein

the shared buffer resource includes a generic buffer region configured to store both initiator and responder transaction packets and one or more initiator regions configured to store only initiator transaction packets, and

the step of stopping only stops issuance of initiator transaction packets directed to the generic buffer region, thereby permitting continued issuance of initiator transaction packets directed to the one or more initiator regions.

3. The method of

claim 2

wherein the shared buffer resource subject to flow control is disposed at a global input port.

4. The method of

claim 3

further comprising the step of decrementing the initiate counter in response to receiving an acknowledgement from the global input port that the initiator transaction packet has been removed from the shared buffer resource.

5. The method of

claim 4

wherein

each node of the multiprocessor system includes at least one global input port and at least one global output port,

the hierarchical switch includes at least one output port associated with each global input port,

a separate initiate counter is provided for each global input port, and

when an initiator transaction packet is issued from the hierarchical switch to a given global input port, the respective initiate counter is incremented.

6. The method of

claim 5

wherein the initiate flow control signal is asserted whenever any of the initiate counters at the hierarchical switch exceeds the predefined threshold.

7. The method of

claim 6

further comprising the step of deasserting the initiate flow control signal provided that all of the initiate counters are below the predefined threshold.

8. The method of

claim 7

wherein the flow control signal is received at an arbiter at each global output port, and, if asserted, triggers the arbiter to prevent the global output port from issuing further initiator transaction packets to the generic buffer region of the shared buffer resource.

9. The method of

claim 8

further comprising the step of providing absolute priority to the issuance of responder transaction packets over initiator transaction packets, in response to the assertion of the initiate flow control signal.

10. The method of

claim 9

wherein

the initiator transaction packets include programmed input/output (I/O) read and write transactions (QIO), processor command requests for memory space read transactions (Q0), and processor command requests for memory space write transaction (Q0Vic), and

the responder transaction packets include ordered and unordered responses to QIO, Q0 and Q0Vic requests.

11. The method of

claim 10

wherein the one or more initiator regions of the shared buffer resource include a forward progress guarantee region configured to store QIO initiator transaction packets and a portion of a deadlock avoidance region configured to store Q0 and Q0Vic initiator transaction packets.

12. A switch fabric for interconnecting a plurality of nodes of a modular multi-processor system, the nodes configured to source and receive initiator and responder transaction packets, the switch fabric comprising:

a shared buffer resource for storing transaction packets received by a node of the multiprocessor system;

at least one initiate counter that is incremented each time an initiator transaction packet is issued to the shared buffer resource;

an initiate flow control circuit coupled to the at least one initiate counter, the initiate flow control circuit configured to assert an initiate flow control signal whenever the initiate counter exceeds a predefined threshold; and

means, responsive to the assertion of the initiate flow control signal, for stopping the nodes of the multiprocessor system from issuing at least some initiator transaction packets, but permitting the nodes to continue issuing responder transaction packets.

13. The switch fabric of

claim 12

wherein the shared buffer resource includes a generic buffer region configured to store both initiator and responder transaction packets and one or more initiator regions configured to store only initiator transaction packets, and

the means for stopping only stops issuance of initiator transaction packets directed to the generic buffer region, thereby permitting continued issuance of initiator transaction packets directed to the one or more initiator regions.

14. The switch fabric of

claim 13

wherein the at least one initiate counter is decremented in response to an acknowledgement indicating that an initiator transaction packet has been removed from the shared buffer resource.

15. The switch fabric of

claim 14

wherein

each node of the multiprocessor system includes a shared buffer resource,

an initiate counter is associated with each shared buffer resource,

the initiate flow control circuit asserts the initiate flow control signal whenever any of the initiate counters exceeds the predefined threshold.

16. The switch fabric of

claim 15

wherein the initiate flow control circuit deasserts the initiate flow control signal provided that all of the initiate counters are below the predefined threshold.

17. The switch fabric of

claim 16

further comprising an arbiter disposed at each global output port, and configured to receive the initiate flow control signal and to prevent the global output port from issuing further initiator transaction packets to the generic buffer region of the shared buffer resource, if the initiate flow control signal is asserted.

18. The switch fabric of

claim 17

wherein the arbiter grants absolute priority to the issuance of responder transaction packets over initiator transaction packets, in response to the assertion of the initiate flow control signal.