Data management architecture

• US 20010056520A1
• Filed: 06/14/2001
• Published: 12/27/2001
• Est. Priority Date: 06/15/2000
• Status: Active Grant

• Current Assignee: DataDirect Networks Incorporated
• Original Assignee: DataDirect Networks Incorporated
• Inventors: Williams, Richard, Piszczek, Michael, McBryde, Lee, Illar, Dave, Manning, Gordon
• Granted Patent: US 7,127,668 B2
• Time in Patent Office: Days
• US Class Current: 711/114
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 2211/1009 Cache, i.e. caches used in RAID system with parity
• CPC Class Codes: G06F 2211/1054 Parity-fast hardware, i.e. dedicated fast hardware for RAID systems with parity

Abstract

A performance optimized RAID Level 3 storage access controller with a unique XOR engine placement at the host/network side of the cache. The invention utilizes multiple data communications channels and a centralized cache memory in conjunction with this unique XOR placement to maximize performance and fault tolerance between a host network and data storage. Positioning the XOR engine at the host/network side of the cache allows the storage devices to be fully independent. Since the XOR engine is placed in the data path and the parity is generated in real-time during cache write transfers, the bandwidth overhead is reduced to zero. For high performance RAID controller applications, a system architecture with minimal bandwidth overhead provides superior performance.

Claims

1. A data management architecture comprising:

a) an XOR engine;

b) a host network interface coupled to said XOR engine and for coupling to a host computer system;

c) a cache coupled to said XOR engine;

d) a storage device interface coupled to said cache and for coupling to a plurality of storage devices.

2. The data management architecture defined by

claim 1

wherein said XOR engine comprises:

a) a first transceiver coupled to said host network interface;

b) logic means for i) generating an XOR parity byte using said data and appending said parity byte to said data, ii) checking XOR parity, and iii) correcting detected parity errors;

c) a second transceiver coupled to said cache .

3. The data management architecture defined by

claim 1

wherein said host network interface comprises:

a) a physical interface;

b) a protocol engine coupled to the physical interface;

c) a receive buffer coupled to the protocol engine;

d) a transmit buffer coupled to the protocol engine;

e) interface buffers coupled to the transmit and receive buffers;

f) a bus coupled to the protocol engine;

g) a microcontroller coupled to the bus;

h) a memory coupled to the bus.

4. The data management architecture defined by

claim 1

wherein said cache comprises:

a plurality of cache segments, each of said cache segments including i) a dual port memory array, ii) a bus expander coupled between said XOR engine and said dual port memory array, iii) a bus funnel coupled between said XOR engine and said dual port memory array, and iv) a buffer coupled between said storage device interface and said dual port memory.

5. The data management architecture defined by

claim 1

wherein said storage device interface comprises:

a) a physical interface;

b) a protocol engine coupled to the physical interface;

c) a receive buffer coupled to the protocol engine;

d) a transmit buffer coupled to the protocol engine;

e) interface buffers coupled to the transmit and receive buffers;

f) a bus coupled to the protocol engine;

g) a microcontroller coupled to the bus;

h) a memory coupled to the bus.

6. A data management architecture comprising:

a) an XOR engine;

b) a host network interface coupled to said XOR engine and for coupling to a host computer system;

c) a cache coupled to said XOR engine;

d) a storage device interface coupled to said cache and for coupling to a plurality of storage devices,

wherein said XOR engine includes;

a first transceiver coupled to said host network interface;

logic means for i) generating an XOR parity byte using said data and appending said parity byte to said data, ii) checking XOR parity, and iii) correcting detected parity errors;

a second transceiver coupled to said cache.

7. A data management architecture comprising:

a) an XOR engine;

b) a host network interface coupled to said XOR engine and for coupling to a host computer system;

c) a cache coupled to said XOR engine, said cache including a plurality of cache segments, each of said cache segments including i) a dual port memory array, ii) a bus expander coupled between said XOR engine and said dual port memory array, iii) a bus funnel coupled between said XOR engine and said dual port memory array, and iv) a buffer coupled between said storage device interface and said dual port memory;

d) a storage device interface coupled to said cache and for coupling to a plurality of storage devices,

wherein said XOR engine includes;

a first transceiver coupled to said host network interface;

logic means for i) generating an XOR parity byte using said data and appending said parity byte to said data, ii) checking XOR parity, and iii) correcting detected parity errors;

a second transceiver coupled to said cache.