SECURE MEMORY AREA

• US 20010056540A1
• Filed: 09/16/1998
• Published: 12/27/2001
• Est. Priority Date: 09/16/1997
• Status: Abandoned Application

• Current Assignee: SafeNet Incorporated (Thales SA)
• Original Assignee: SafeNet Incorporated (Thales SA)
• Inventors: REED, PETER, OBER, TIMOTHY
• Application Number:
  US09/154,300
• Publication Number:
  US 20010056540A1
• Time in Patent Office: Days
• US Class Current: 713/193
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 21/82 Protecting input, output or interconnection devices
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices

Abstract

A hardware secure memory area includes one or more secondary communication buses connected to a main communication bus. The secondary communication buses are coupled to the main communication bus by separate bus transceivers. The bus transceivers provide isolation between the communication buses and between unaccessed secondary buses and the main communication buses. Various external devices, such as memories, may be coupled to the communication buses. Only one bus transceiver may be activated at a time, thus making it impossible for two secondary communication buses to be linked.

Claims

1. A hardware secure memory area, which comprises:

a main communication bus;

a plurality of secondary communication buses;

a plurality of bus transceivers coupling the plurality of secondary communication buses to the main communication bus; and

a plurality of memory circuits coupled to the plurality of communication buses, each bus transceiver selectively isolating a secondary communication bus to which the bus transceiver is associated from the main communication bus and selectively causing communication between the associated secondary communication bus and the main communication bus.

2. A hardware secure memory area, which comprises:

a main communication bus;

a first bus transceiver coupled to the main communication bus;

a second bus transceiver coupled to the main communication bus;

a third bus transceiver coupled to the main communication bus;

a key communication bus coupled to the first bus transceiver;

a key cache coupled to the key communication bus for writing and reading keys;

a key random access memory coupled to the key communication bus for writing and reading cryptographic operations and keys;

a processor memory for writing and reading cryptographic algorithms, operations and keys;

an external memory communication bus coupled to the second bus transceiver;

an external memory coupled to the external memory communication bus for writing and reading application programs and commands;

a cryptographic algorithm communication bus coupled to the third bus transceiver;

a scratch memory coupled to the cryptographic algorithm communication bus for writing and reading cryptographic calculations; and

a memory coupled to the cryptographic algorithm communication bus for storing cryptographic algorithms.

3. A hardware secure memory area, which comprises:

a main communication bus;

a plurality of bus transceivers coupled to the main communication bus for controlling access to and from the main communication bus;

a plurality of secondary communication buses coupled to the bus transceivers; and

a plurality of memory circuits coupled to the plurality of secondary communication buses.