Error control apparatus and method using cyclic code
First Claim
1. An error control circuit including:
- a deinterleaver for deinterleaving data of a predetermined number of bits coded by predetermined cyclic codes and to be interleaved in accordance with a predetermined interleave order;
a first cyclic code checking circuit for receiving an output of said deinterleaver and conducting a cyclic code check on said data of the predetermined number of bits by a check system corresponding to a coding system of said cyclic code; and
a second cyclic code checking circuit for receiving an output of said deinterleaver and conducting a cyclic code check on said data of the predetermined number of bits by a check system corresponding to the coding system of said cyclic code simultaneously with the cyclic code check by said first cyclic code checking circuit in substantially the same time while canceling an interleave effect by said deinterleaver.
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Accused Products
Abstract
An error control apparatus includes: a deinterleaver for deinterleaving data of a predetermined number of bits coded by predetermined cyclic codes, which is to be interleaved in accordance with a predetermined interleaving order; a first cyclic code checking circuit for receiving an output of the deinterleaver and making a cyclic code check on the data of the predetermined number of bits by a check system corresponding to a coding system of the cyclic code; and a second cyclic code checking circuit for receiving an output of the deinterleaver and making a cyclic code check on the data of the predetermined number of bits by a check system corresponding to the coding system of the cyclic code simultaneously with the cyclic code check by the first cyclic code checking circuit in substantially the same time while canceling an interleave effect by the deinterleaver.
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Citations
14 Claims
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1. An error control circuit including:
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a deinterleaver for deinterleaving data of a predetermined number of bits coded by predetermined cyclic codes and to be interleaved in accordance with a predetermined interleave order;
a first cyclic code checking circuit for receiving an output of said deinterleaver and conducting a cyclic code check on said data of the predetermined number of bits by a check system corresponding to a coding system of said cyclic code; and
a second cyclic code checking circuit for receiving an output of said deinterleaver and conducting a cyclic code check on said data of the predetermined number of bits by a check system corresponding to the coding system of said cyclic code simultaneously with the cyclic code check by said first cyclic code checking circuit in substantially the same time while canceling an interleave effect by said deinterleaver. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An error control method including:
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a step of deinterleaving data of a predetermined number of bits coded by predetermined cyclic codes and to be interleaved in accordance with a predetermined interleaving order;
a step of receiving data deinterleaved in said deinterleaving step, and conducting a first cyclic code check on said data of the predetermined number of bits by a check system corresponding to a coding system of said cyclic code; and
a step of receiving said deinterleaved data and conducting a second cyclic code check on said data of the predetermined number of bits by a check system corresponding to the coding system of said cyclic code simultaneously with the step of conducting said first cyclic code check in substantially the same time. - View Dependent Claims (13, 14)
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9. An error control method,
wherein said step for conducting said second cyclic code check includes: -
a step of initializing a plurality of temporary cyclic check data holding means of the number corresponding to the maximum degree of a polynomial of generating said cyclic code; and
a step of calculating a check bit in each of positions of said cyclic codes by performing a computation sequence made by a plurality of clock cycle computations determined by a coding system of said cyclic code and said interleave system on data deinterleaved in said deinterleaving step while using said plurality of temporary cyclic check data holding means. - View Dependent Claims (10, 11, 12)
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Specification