Display device

• US 20020000576A1
• Filed: 06/22/2001
• Published: 01/03/2002
• Est. Priority Date: 06/22/2000
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Inukai, Kazutaka
• Granted Patent: US 7,053,890 B2
• Time in Patent Office: Days
• US Class Current: 257/202
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays

Abstract

An active matrix display device capable of vivid color display having many tones is provided. The display device is characterized in that each of a plurality of pixels comprises a first TFT for switching, a second TFT for switching, a TFT for erasing, a TFT for EL driving, and an EL element, driving of the TFT for EL driving is controlled by the first TFT for switching, the second TFT for switching, and the TFT for erasing, and light emission by the EL element is controlled by the TFT for EL driving.

Claims

1. A display device comprising:

a plurality of gate signal lines and

a plurality of pixels, each of said plurality of pixels controlled by at least one of said plurality of gate signal lines, wherein;

each of said plurality of pixels comprises a first TFT for switching, a second TFT for switching, a TFT for erasing, a TFT for electroluminescence driving, and an electroluminescence element;

switching of said TFT for erasing is controlled by voltage applied to a kth gate signal line of said plurality of gate signal lines (where k is a natural number);

switching of said first TFT for switching is controlled by voltage applied to a (k+1)th gate signal line of said plurality of gate signal lines;

switching of said second TFT for switching is controlled by voltage applied to a (k+2)th gate signal line of said plurality of gate signal lines;

a digital video signal is inputted to a gate electrode of said TFT for electroluminescence driving when both said first TFT for switching and said second TFT for switching are ON;

switching of said TFT for electroluminescence driving is controlled by said digital video signal;

said TFT for electroluminescence driving is turned off when said TFT for erasing is turned on; and

said electroluminescence element emits light when said TFT for electroluminescence driving is ON and does not emit light when said TFT for electroluminescence driving is off.

47. A display device according to claim 1, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are n-channel TFTs.

56. A display device according to claim 1, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are p-channel TFTs.

65. A display device according to claim 1, wherein said TFT Id for electroluminescence driving is driven in a linear region.

74. A display device according to claim 1, wherein said display device is a device selected from the group of consisting:

a computer, a video camera and a DVD player.

2. A display device comprising:

a plurality of source signal lines;

a plurality of gate signal lines crossing said plurality of gate signal lines;

a plurality of power supply lines along said plurality of gate signal lines of said plurality of source signal lines; and

a plurality of pixels disposed in matrix-form, wherein;

each of said plurality of pixels comprises a first TFT for switching, a second TFT for switching, a TFT for erasing, a TFT for electroluminescence driving, and an electroluminescence element;

a gate electrode of said TFT for erasing is connected to a kth gate signal line of said plurality of gate signal lines, wherein k is a natural number;

a gate electrode of said first TFT for switching is connected to a (k+1)th gate signal line of said plurality of gate signal lines;

a gate electrode of said second TFT for switching is connected to a (k+2)th gate signal line of said plurality of gate signal lines;

one of a source region and a drain region of said second TFT for switching is connected to one of said plurality of source signal lines and the other is connected to a source region or a drain region of said first TFT for switching;

said source region or drain region of said first TFT for switching not connected to said source region or drain region of said second TFT for switching is connected to a gate electrode of said TFT for electroluminescence driving;

one of a source region and a drain region of said TFT for erasing is connected to one of said plurality of power supply lines and the other is connected to said gate electrode of said TFT for electroluminescence driving; and

a source region of said TFT for electroluminescence driving is connected to one of said plurality of power supply lines and a drain region of said TFT for electroluminescence driving is connected to said electroluminescence element.

31. A display device according to claim 2, further comprising:

gate wiring connected to said gate electrode of said TFT for electroluminescence driving; and

capacity wiring connected to one of said plurality of power supply lines,

wherein a gate insulating film of said first TFT for switching, said second TFT for switching, said TFT for erasing, and said TFT for electroluminescence driving is provided between said gate wiring and said capacity wiring.

39. A display device according to claim 2, wherein:

two of said plurality of pixels disposed along a direction of provision of said plurality of gate signal lines are adjacent to each other with sandwiching any one of said plurality of power supply lines therebetween and said respective source regions of said TFTs for electroluminescence driving of said two pixels are connected to said one of said plurality of power supply lines.

48. A display device according to claim 2, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are n-channel TFTs.

57. A display device according to claim 2, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are p-channel TFTs.

66. A display device according to claim 2, wherein said TFT for electroluminescence driving is driven in a linear region.

75. A display device according to claim 2, wherein said display device is a device selected from the group of consisting:

a computer, a video camera and a DVD player.

3. A display device comprising:

a plurality of source signal lines;

a plurality of gate signal lines crossing said plurality of gate signal lines;

a plurality of power supply lines along said plurality of gate signal lines of said plurality of source signal lines; and

a plurality of pixels disposed in matrix-form, wherein;

each of said plurality of pixels comprises a first TFT for switching, a second TFT for switching, a TFT for erasing, a TFT for electroluminescence driving, and an electroluminescence element;

a gate electrode of said TFT for erasing is connected to a kth gate signal line of said plurality of gate signal lines, (wherein k is a natural number);

a gate electrode of said first TFT for switching is connected to a (k+2)th gate signal line of said plurality of gate signal lines;

a gate electrode of said second TFT for switching is connected to a (k+1)th gate signal line of said plurality of gate signal lines;

one of a source region and a drain region of said second TFT for switching is connected to one of said plurality of source signal lines and the other is connected to a source region or a drain region of said first TFT for switching;

said source region or drain region of said first TFT for switching not connected to said source region or drain region of said second TFT for switching is connected to a gate electrode of said TFT for electroluminescence driving;

one of a source region and a drain region of said TFT for erasing is connected to one of said plurality of power supply lines and the other is connected to said gate electrode of said TFT for electroluminescence driving; and

a source region of said TFT for electroluminescence driving is connected to one of said plurality of power supply lines and a drain region of said TFT for electroluminescence driving is connected to said electroluminescence element.

32. A display device according to claim 3, further comprising:

gate wiring connected to said gate electrode of said TFT for electroluminescence driving; and

capacity wiring connected to one of said plurality of power supply lines,

wherein a gate insulating film of said first TFT for switching, said second TFT for switching, said TFT for erasing, and said TFT for electroluminescence driving is provided between said gate wiring and said capacity wiring.

40. A display device according to claim 3, wherein:

two of said plurality of pixels disposed along a direction of provision of said plurality of gate signal lines are adjacent to each other with sandwiching any one of said plurality of power supply lines therebetween and said respective source regions of said TFTs for electroluminescence driving of said two pixels are connected to said one of said plurality of power supply lines.

49. A display device according to claim 3, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are n-channel TFTs.

58. A display device according to claim 3, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are p-channel TFTs.

67. A display device according to claim 3, wherein said TFT for electroluminescence driving is driven in a linear region.

76. A display device according to claim 3, wherein said display device is a device selected from the group of consisting:

a computer, a video camera and a DVD player.

4. A display device comprising:

a plurality of source signal lines;

a plurality of gate signal lines crossing said plurality of gate signal lines;

a plurality of power supply lines along said plurality of gate signal lines of said plurality of source signal lines; and

a plurality of pixels disposed in matrix-form, wherein;

each of said plurality of pixels comprises a first TFT for switching, a second TFT for switching, a TFT for erasing, a TFT for electroluminescence driving, and an electroluminescence element;

said electroluminescence element comprises an anode, a cathode, and an electroluminescence layer provided between said anode and said cathode;

a gate electrode of said TFT for erasing is connected to a kth gate signal line of said plurality of gate signal lines (where k is a natural number);

a gate electrode of said first TFT for switching is connected to a (k+1)th gate signal line of said plurality of gate signal lines;

a gate electrode of said second TFT for switching is connected to a (k+2)th gate signal line of said plurality of gate signal lines;

one of a source region and a drain region of said second TFT for switching is connected to one of said plurality of source signal lines and the other is connected to a source region or a drain region of said first TFT for switching;

said source region or drain region of said first TFT for switching not connected to said source region or drain region of said second TFT for switching is connected to a gate electrode of said TFT for electroluminescence driving;

one of a source region and a drain region of said TFT for erasing is connected to one of said plurality of power supply lines and the other is connected to said gate electrode of said TFT for electroluminescence driving;

a source region of said TFT for electroluminescence driving is connected to one of said plurality of power supply lines and a drain region of said TFT for electroluminescence driving is connected to said anode; and

said TFT for electroluminescence driving is a p-channel TFT.

6. A display device according to claim 4, wherein said electroluminescence layer is formed of a small molecular organic substance or a polymer organic material.

8. A display device according to claim 6, wherein said small molecular organic material is formed of Alq₃ (tris-8-quinolinolate-aluminum) or a TPD (triphenylamine derivative).

10. A display device according to claim 6, wherein said polymer organic material is formed of PPV (polyphenylene vinylene), PVK (polyvinyl carbazole), or polycarbonate.

12. A display device according to claim 4, wherein:

said anode or cathode is connected directly or through at least one wiring to said drain region of said TFT for electroluminescence driving; and

a bank is formed over a region where said anode or cathode is connected to said drain region of said TFT for electroluminescence driving or to said at least one wiring.

33. A display device according to claim 4, further comprising:

gate wiring connected to said gate electrode of said TFT for electroluminescence driving; and

capacity wiring connected to one of said plurality of power supply lines,

wherein a gate insulating film of said first TFT for switching, said second TFT for switching, said TFT for erasing, and said TFT for electroluminescence driving is provided between said gate wiring and said capacity wiring.

41. A display device according to claim 4, wherein:

two of said plurality of pixels disposed along a direction of provision of said plurality of gate signal lines are adjacent to each other with sandwiching any one of said plurality of power supply lines therebetween and said respective source regions of said TFTs for electroluminescence driving of said two pixels are connected to said one of said plurality of power supply lines.

50. A display device according to claim 4, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are n-channel TFTs.

59. A display device according to claim 4, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are p-channel TFTs.

68. A display device according to claim 4, wherein said TFT for electroluminescence driving is driven in a linear region.

77. A display device according to claim 4, wherein said display device is a device selected from the group of consisting:

a computer, a video camera and a DVD player.

5. A display device comprising:

a plurality of source signal lines;

a plurality of gate signal lines crossing said plurality of gate signal lines;

a plurality of power supply lines along said plurality of gate signal lines of said plurality of source signal lines; and

a plurality of pixels disposed in matrix-form, wherein;

each of said plurality of pixels comprises a first TFT for switching, a second TFT for switching, a TFT for erasing, a TFT for electroluminescence driving, and an electroluminescence element;

said electroluminescence element comprises an anode, a cathode, and an electroluminescence layer provided between said anode and said cathode;

a gate electrode of said TFT for erasing is connected to a kth gate signal line of said plurality of gate signal lines (where k is a natural number);

a gate electrode of said first TFT for switching is connected to a (k+1)th gate signal line of said plurality of gate signal lines;

a gate electrode of said second TFT for switching is connected to a (k+2)th gate signal line of said plurality of gate signal lines;

one of a source region and a drain region of said second TFT for switching is connected to one of said plurality of source signal lines and the other is connected to a source region or a drain region of said first TFT for switching;

said source region or drain region of said first TFT for switching not connected to said source region or drain region of said second TFT for switching is connected to a gate electrode of said TFT for electroluminescence driving;

one of a source region and a drain region of said TFT for erasing is connected to one of said plurality of power supply lines and the other is connected to said gate electrode of said TFT for electroluminescence driving;

a source region of said TFT for electroluminescence driving is connected to one of said plurality of power supply lines and a drain region of said TFT for electroluminescence driving is connected to said cathode; and

said TFT for electroluminescence driving is an n-channel TFT.

7. A display device according to claim 5, wherein said electroluminescence layer is formed of a small molecular organic substance or a polymer organic material.

9. A display device according to claim 7, wherein said small molecular organic material is formed of Alq₃ (tris-8-quinolinolate-aluminum) or a TPD (triphenylamine derivative).

11. A display device according to claim 7, wherein said polymer organic material is formed of PPV (polyphenylene vinylene), PVK (polyvinyl carbazole), or polycarbonate.

13. A display device according to claim 5, wherein:

said anode or cathode is connected directly or through at least one wiring to said drain region of said TFT for electroluminescence driving; and

a bank is formed over a region where said anode or cathode is connected to said drain region of said TFT for electroluminescence driving or to said at least one wiring.

14. A display device according to claim 9, wherein said bank has a light blocking property.

34. A display device according to claim 5, further comprising:

gate wiring connected to said gate electrode of said TFT for electroluminescence driving; and

capacity wiring connected to one of said plurality of power supply lines,

wherein a gate insulating film of said first TFT for switching, said second TFT for switching, said TFT for erasing, and said TFT for electroluminescence driving is provided between said gate wiring and said capacity wiring.

42. A display device according to claim 5, wherein:

two of said plurality of pixels disposed along a direction of provision of said plurality of gate signal lines are adjacent to each other with sandwiching any one of said plurality of power supply lines therebetween and said respective source regions of said TFTs for electroluminescence driving of said two pixels are connected to said one of said plurality of power supply lines.

51. A display device according to claim 5, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are n-channel TFTs.

60. A display device according to claim 5, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are p-channel TFTs.

69. A display device according to claim 5, wherein said TFT for electroluminescence driving is driven in a linear region.

78. A display device according to claim 5, wherein said display device is a device selected from the group of consisting:

a computer, a video camera and a DVD player.

15. A display device comprising:

a plurality of source signal lines;

a plurality of gate signal lines crossing said plurality of gate signal lines;

a plurality of power supply lines along said plurality of gate signal lines of said plurality of source signal lines; and

a plurality of pixels disposed in matrix-form, wherein;

each of said plurality of pixels comprises a first TFT for switching, a second TFT for switching, a TFT for erasing, a TFT for electroluminescence driving, and an electroluminescence element;

a gate electrode of said TFT for erasing is connected to a kth gate signal line of said plurality of gate signal lines (where k is a natural number);

a gate electrode of said first TFT for switching is connected to a (k+1)th gate signal line of said plurality of gate signal lines;

a gate electrode of said second TFT for switching is connected to a (k+2)th gate signal line of said plurality of gate signal lines;

one of a source region and a drain region of said second TFT for switching is connected to one of said plurality of source signal lines and the other is connected to a source region or a drain region of said first TFT for switching;

said source region or drain region of said first TFT for switching not connected to said source region or drain region of said second TFT for switching is connected to a gate electrode of said TFT for electroluminescence driving;

one of a source region and a drain region of said TFT for erasing is connected to one of said plurality of power supply lines and the other is connected to said gate electrode of said TFT for electroluminescence driving;

a source region of said TFT for electroluminescence driving is connected to one of said plurality of power supply lines and a drain region of said TFT for electroluminescence driving is connected to said electroluminescence element;

a plurality of writing periods Ta and a plurality of erasing periods Te are provided in one frame period;

said plurality of gate signal lines are sequentially selected according to a first selection signal sequentially inputted to said plurality of gate signal lines during said plurality of writing periods Ta;

said plurality of gate signal lines are serially selected according to a second selection signal serially inputted to said plurality of gate signal lines during said plurality of erasing periods Te;

a period where a gate signal line is selected from said plurality of gate signal lines according to said first selection signal and a period where an adjacent gate signal line is selected overlap each other;

a period where a gate signal line is selected from said plurality of gate signal lines according to said second selection signal and a period where an adjacent gate signal line is selected do not overlap each other; and

a period where an arbitrary gate signal line is selected from said plurality of gate signal lines according to said first selection signal is twice as long as a period where said gate signal line is selected according to said second selection signal.

23. A display device according to claim 15, wherein said plurality of writing periods Ta do not overlap each other.

27. A display device according to claim 15, wherein said plurality of erasing periods Te do not overlap each other.

35. A display device according to claim 15, further comprising:

gate wiring connected to said gate electrode of said TFT for electroluminescence driving; and

capacity wiring connected to one of said plurality of power supply lines,

wherein a gate insulating film of said first TFT for switching, said second TFT for switching, said TFT for erasing, and said TFT for electroluminescence driving is provided between said gate wiring and said capacity wiring.

43. A display device according to claim 15, wherein:

two of said plurality of pixels disposed along a direction of provision of said plurality of gate signal lines are adjacent to each other with sandwiching any one of said plurality of power supply lines therebetween and said respective source regions of said TFTs for electroluminescence driving of said two pixels are connected to said one of said plurality of power supply lines.

52. A display device according to claim 15, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are n-channel TFTs.

61. A display device according to claim 15, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are p-channel TFTs.

70. A display device according to claim 15, wherein said TFT for electroluminescence driving is driven in a linear region.

79. A display device according to claim 15, wherein said display device is a device selected from the group of consisting:

a computer, a video camera and a DVD player.

16. A display device comprising:

a plurality of source signal lines;

a plurality of gate signal lines crossing said plurality of gate signal lines;

a plurality of power supply lines along said plurality of gate signal lines of said plurality of source signal lines; and

a plurality of pixels disposed in matrix-form, wherein;

each of said plurality of pixels comprises a first TFT for switching, a second TFT for switching, a TFT for erasing, a TFT for electroluminescence driving, and an electroluminescence element;

a gate electrode of said TFT for erasing is connected to a kth gate signal line of said plurality of gate signal lines (where k is a natural number);

a gate electrode of said first TFT for switching is connected to a (k+1)th gate signal line of said plurality of gate signal lines;

a gate electrode of said second TFT for switching is connected to a (k+2)th gate signal line of said plurality of gate signal lines;

one of a source region and a drain region of said second TFT for switching is connected to one of said plurality of source signal lines and the other is connected to a source region or a drain region of said first TFT for switching;

said source region or drain region of said first TFT for switching not connected to said source region or drain region of said second TFT for switching is connected to a gate electrode of said TFT for electroluminescence driving;

one of a source region and a drain region of said TFT for erasing is connected to one of said plurality of power supply lines and the other is connected to said gate electrode of said TFT for electroluminescence driving;

a source region of said TFT for electroluminescence driving is connected to one of said plurality of power supply lines and a drain region of said TFT for electroluminescence driving is connected to said electroluminescence element;

a plurality of writing periods Ta and a plurality of erasing periods Te are provided in one frame period;

said plurality of gate signal lines are serially selected according to a first selection signal serially inputted to said plurality of gate signal lines during said plurality of writing periods Ta;

said plurality of gate signal lines are serially selected according to a second selection signal serially inputted to said plurality of gate signal lines during said plurality of erasing periods Te;

a period where a gate signal line is selected from said plurality of gate signal lines according to said first selection signal and a period where an adjacent gate signal line is selected overlap each other;

a period where a gate signal line is selected from said plurality of gate signal lines according to said second selection signal and a period where an adjacent gate signal line is selected do not overlap each other;

a digital video signal is inputted to said plurality of source signal lines during a period where said plurality of gate signal lines are selected according to said first selection signal; and

a period where an arbitrary gate signal line is selected from said plurality of gate signal lines according to said first selection signal is twice as long as a period where said gate signal line is selected according to said second selection signal.

24. A display device according to claim 16, wherein said plurality of writing periods Ta do not overlap each other.

28. A display device according to claim 16, wherein said plurality of erasing periods Te do not overlap each other.

36. A display device according to claim 16, further comprising:

gate wiring connected to said gate electrode of said TFT for electroluminescence driving; and

capacity wiring connected to one of said plurality of power supply lines,

wherein a gate insulating film of said first TFT for switching, said second TFT for switching, said TFT for erasing, and said TFT for electroluminescence driving is provided between said gate wiring and said capacity wiring.

44. A display device according to claim 16, wherein:

two of said plurality of pixels disposed along a direction of provision of said plurality of gate signal lines are adjacent to each other with sandwiching any one of said plurality of power supply lines therebetween and said respective source regions of said TFTs for electroluminescence driving of said two pixels are connected to said one of said plurality of power supply lines.

53. A display device according to claim 16, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are n-channel TFTs.

62. A display device according to claim 16, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are p-channel TFTs.

71. A display device according to claim 16, wherein said TFT for electroluminescence driving is driven in a linear region.

80. A display device according to claim 16, wherein said display device is a device selected from the group of consisting:

a computer, a video camera and a DVD player.

17. A display device comprising:

a plurality of source signal lines;

a plurality of gate signal lines crossing said plurality of gate signal lines;

a plurality of power supply lines along said plurality of gate signal lines of said plurality of source signal lines; and

a plurality of pixels disposed in matrix-form, wherein;

each of said plurality of pixels comprises a first TFT for switching, a second TFT for switching, a TFT for erasing, a TFT for electroluminescence driving, and an electroluminescence element;

a gate electrode of said TFT for erasing is connected to a kth gate signal line of said plurality of gate signal lines (where k is a natural number);

a gate electrode of said first TFT for switching is connected to a (k+1) th gate signal line of said plurality of gate signal lines;

a gate electrode of said second TFT for switching is connected to a (k+2) th gate signal line of said plurality of gate signal lines;

one of a source region and a drain region of said second TFT for switching is connected to one of said plurality of source signal lines and the other is connected to a source region or a drain region of said first TFT for switching;

said source region or drain region of said first TFT for switching not connected to said source region or drain region of said second TFT for switching is connected to a gate electrode of said TFT for electroluminescence driving;

one of a source region and a drain region of said TFT for erasing is connected to one of said plurality of power supply lines and the other is connected to said gate electrode of said TFT for electroluminescence driving;

a source region of said TFT for electroluminescence driving is connected to one of said plurality of power supply lines and a drain region of said TFT for electroluminescence driving is connected to said electroluminescence element;

n writing periods Ta1, Ta2, . . . , and Tan and (m−

1) erasing periods Te1, Te2, . . . , and Te(m−

1) are provided in one frame period (where m is an arbitrary number from 2 to n);

a digital video signal is inputted to said gate electrodes of said TFTs for electroluminescence driving during said writing periods Ta1, Ta2, . . . , and Tan;

said digital video signal inputted to said gate electrodes of said TFTs for electroluminescence driving is erased during said erasing periods Te1, Te2, . . . , and Te(m−

1);

periods from the start of said writing periods Ta1, Ta2, . . . , and Tan to the start of writing periods or erasing periods appearing subsequently to said writing periods Ta1, Ta2, . . . , and Tan are display periods Tr1, Tr2, . . . , and Tr(m−

1), respectively;

periods from the start of said erasing periods Te1, Te2, . . . , and Te(m−

1) to the start of writing periods appearing subsequently to said erasing periods Te1, Te2, . . . , and Te(m−

1) are non-display periods Td1, Td2, . . . , and Tdn, respectively;

whether said electroluminescence elements emit light or not during said display periods Tr1, Tr2, . . . , and Trn is selected according to said digital video signal; and

ratio of lengths of said display periods Tr1, Tr2, . . . , and Trn is represented as 2⁰;

2¹;

. . . ;

2<sup>(n−

1</sup>).

19. A display device according to claim 17, wherein said display periods Tr1, Tr2, . . . , and Trn appear in random order.

21. A display device according to claim 17, wherein a longest non-display period among said non-display periods Td1, Td2, . . . , and Tdn appears last in one frame period.

25. A display device according to claim 17, wherein said writing periods Ta1, Ta2, . . . , and Tan do not overlap each other.

29. A display device according to claim 17, wherein said erasing periods Te1, Te2, . . . , and Te(m−

1) do not overlap each other.

37. A display device according to claim 17, further comprising:

gate wiring connected to said gate electrode of said TFT for electroluminescence driving; and

capacity wiring connected to one of said plurality of power supply lines,

wherein a gate insulating film of said first TFT for switching, said second TFT for switching, said TFT for erasing, and said TFT for electroluminescence driving is provided between said gate wiring and said capacity wiring.

45. A display device according to claim 17, wherein:

two of said plurality of pixels disposed along a direction of provision of said plurality of gate signal lines are adjacent to each other with sandwiching any one of said plurality of power supply lines therebetween and said respective source regions of said TFTs for electroluminescence driving of said two pixels are connected to said one of said plurality of power supply lines.

54. A display device according to claim 17, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are n-channel TFTs.

63. A display device according to claim 17, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are p-channel TFTs.

72. A display device according to claim 17, wherein said TFT for electroluminescence driving is driven in a linear region.

81. A display device according to claim 17, wherein said display device is a device selected from the group of consisting:

a computer, a video camera and a DVD player.

18. A display device comprising:

it a plurality of source signal lines;

a plurality of gate signal lines crossing said plurality of gate signal lines;

a plurality of power supply lines along said plurality of gate signal lines of said plurality of source signal lines; and

a plurality of pixels disposed in matrix-form, wherein;

each of said plurality of pixels comprises a first TFT for switching, a second TFT for switching, a TFT for erasing, a TFT for electroluminescence driving, and an electroluminescence element;

a gate electrode of said TFT for erasing is connected to a kth gate signal line of said plurality of gate signal lines (where k is a natural number);

a gate electrode of said first TFT for switching is connected to a (k+1)th gate signal line of said plurality of gate signal lines;

a gate electrode of said second TFT for switching is connected to a (k+2)th gate signal line of said plurality of gate signal lines;

one of a source region and a drain region of said second TFT for switching is connected to one of said plurality of source signal lines and the other is connected to a source region or a drain region of said first TFT for switching;

said source region or drain region of said first TFT f or switching not connected to said source region or drain region of said second TFT for switching is connected to a gate electrode of said TFT for electroluminescence driving;

one of a source region and a drain region of said TFT for erasing is connected to one of said plurality of power supply lines and the other is connected to said gate electrode of said TFT for electroluminescence driving;

a source region of said TFT for electroluminescence driving is connected to one of said plurality of power supply lines and a drain region of said TFT for electroluminescence driving is connected to said electroluminescence element;

n writing periods Ta1, Ta2, . . . , and Tan and (m−

1) erasing periods Te1, Te2, . . . , and Te(m−

1) are provided in one frame period (where m is an arbitrary number from 2 to n);

a digital video signal is inputted to said gate electrodes of said TFTs for electroluminescence driving during said writing periods Ta1, Ta2, . . . , and Tan;

said digital video signal inputted to said gate electrodes of said TFTs for electroluminescence driving is erased during said erasing periods Te1, Te2, . . . , and Te(m−

1);

periods from the start of said writing periods Ta1, Ta2, . . . , and Tan to the start of writing periods or erasing periods appearing subsequently to said writing periods Ta1, Ta2, . . . , and Tan are display periods Tr1, Tr2, . . . , and Tr(m−

1), respectively;

periods from the start of said erasing periods Te1, Te2, . . . , and Te(m−

1) to the start of writing periods appearing subsequently to said erasing periods Te1, Te2, . . . , and Te(m−

1) are non-display periods Td1, Td2, . . . , and Tdn, respectively;

whether said electroluminescence elements emit light or not during said display periods Tr1, Tr2, . . . , and Trn is selected according to said digital video signal;

ratio of lengths of said display periods Tr1, Tr2, . . . , and Trn is represented as 2⁰;

2¹;

. . . ;

2⁽ⁿ⁻

1);

said plurality of gate signal lines are serially selected according to a first selection signal serially inputted to said plurality of gate signal lines during said writing periods Ta1, Ta2, . . . , and Tan;

said plurality of gate signal lines are serially selected according to a second selection signal serially inputted to said plurality of gate signal lines during said erasing periods Te1, Te2, . . . , and Te(m−

1);

a period where a gate signal line is selected from said plurality of gate signal lines according to said first selection signal and a period where an adjacent gate signal line is selected overlap each other;

a period where a gate signal line is selected from said plurality of gate signal lines according to said second selection signal and a period where an adjacent gate signal line is selected do not overlap each other; and

a period where an arbitrary gate signal line is selected from id said plurality of gate signal lines according to said first selection signal is twice as long as a period where said gate signal line is selected according to said second selection signal.

20. A display device according to claim 18, wherein said display periods Tr1, Tr2, . . . , and Trn appear in random order.

22. A display device according to claim 18, wherein a longest non-display period among said non-display periods Td1, Td2, . . . , and Tdn appears last in one frame period.

26. A display device according to claim 18, wherein said writing periods Ta1, Ta2, . . . , and Tan do not overlap each other.

30. A display device according to claim 18, wherein said erasing periods Te1, Te2, . . . , and Te(m−

1) do not overlap each other.

38. A display device according to claim 18, further comprising:

gate wiring connected to said gate electrode of said TFT for electroluminescence driving; and

capacity wiring connected to one of said plurality of power supply lines, wherein a gate insulating film of said first TFT for switching, said second TFT for switching, said TFT for erasing, and said TFT for electroluminescence driving is provided between said gate wiring and said capacity wiring.

46. A display device according to claim 18, wherein:

two of said plurality of pixels disposed along a direction of provision of said plurality of gate signal lines are adjacent to each other with sandwiching any one of said plurality of power supply lines therebetween and said respective source regions of said TFTs for electroluminescence driving of said two pixels are connected to said one of said plurality of power supply lines.

55. A display device according to claim 18, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are n-channel TFTs.

64. A display device according to claim 18, wherein said first TFT for switching, said second TFT for switching, and said TFT for erasing are p-channel TFTs.

73. A display device according to claim 18, wherein said TFT for electroluminescence driving is driven in a linear region.

82. A display device according to claim 18, wherein said display device is a device selected from the group of consisting:

a computer, a video camera and a DVD player.