Vacuum package fabrication of integrated circuit components
First Claim
1. A method for vacuum packaging integrated circuit devices, comprising:
- forming on a device wafer a plurality of integrated circuit devices;
forming a plurality of first sealing rings, each of the plurality of first sealing rings surrounding one or more integrated circuit devices, each first sealing ring positioned between the perimeter of the one or more integrated circuit devices and one or more bonding pads coupled to each of the one or more integrated circuit devices;
forming on a lid wafer a plurality of second sealing rings corresponding in number and location to the plurality of first sealing rings;
forming a sealing layer on either each of the plurality of first sealing rings or each of the plurality of second sealing rings;
aligning the device wafer and the lid wafer such that each of the plurality of first sealing rings aligns with the corresponding one of the plurality of second sealing rings leaving a gap between the device wafer and the lid wafer; and
mating the device wafer with the lid wafer in a vacuum environment to form a vacuum package within each of the plurality of first sealing rings and second sealing rings, each vacuum package enclosing one or more of the plurality of integrated circuit devices.
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Accused Products
Abstract
A method for vacuum packaging MEMS or similar devices during device fabrication comprises forming a plurality of MEMS devices (12), or similar devices, on a device wafer (10). A device sealing ring (16) is formed between the MEMS devices (12) and bonding pads (14) connected to a MEMS device. A solder adhesion layer (24) forms part of the device sealing ring (16) surrounding each MEMS or similar device (12). A lid wafer (30) is formed having a plurality of lid sealing rings (32) corresponding in number and location to the device sealing rings (16). Each lid sealing ring (32) surrounds a cavity (34). The device wafer (30) is aligned with the lid wafer (10) to align each device sealing ring (16) with the corresponding lid sealing ring (32), leaving a gap between the lid wafer (30) and the device wafer (10). The resulting assembly (50) is placed in a vacuum furnace. The vacuum furnace is evacuated and heated to a temperature sufficient to allow outgassing of all surface areas of the lid wafer (30) and the device (10). The device wafer (30) is brought into contact with the lid wafer (10) thereby creating a vacuum package over each MEMS device (12). The assembly (50) is cooled at a rate sufficient to minimize subsequent outgassing of the surfaces while minimizing thermal stresses upon the vacuum package. After the assembly (50) is cooled, each vacuum packaged MEMS device (12) is tested, and the assembly (50) is then diced into individual vacuum packaged MEMS devices (12).
170 Citations
32 Claims
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1. A method for vacuum packaging integrated circuit devices, comprising:
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forming on a device wafer a plurality of integrated circuit devices;
forming a plurality of first sealing rings, each of the plurality of first sealing rings surrounding one or more integrated circuit devices, each first sealing ring positioned between the perimeter of the one or more integrated circuit devices and one or more bonding pads coupled to each of the one or more integrated circuit devices;
forming on a lid wafer a plurality of second sealing rings corresponding in number and location to the plurality of first sealing rings;
forming a sealing layer on either each of the plurality of first sealing rings or each of the plurality of second sealing rings;
aligning the device wafer and the lid wafer such that each of the plurality of first sealing rings aligns with the corresponding one of the plurality of second sealing rings leaving a gap between the device wafer and the lid wafer; and
mating the device wafer with the lid wafer in a vacuum environment to form a vacuum package within each of the plurality of first sealing rings and second sealing rings, each vacuum package enclosing one or more of the plurality of integrated circuit devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for vacuum packaging integrated circuit devices, comprising:
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forming on a device wafer a plurality of integrated circuit devices;
forming a plurality of first sealing rings, each of the plurality of first sealing rings surrounding one or more integrated circuit devices, each first sealing ring positioned between the perimeter of the one or more integrated circuit device and one or more bonding pads coupled to each of the one or more integrated circuit devices;
forming on a lid wafer a plurality of second sealing rings corresponding in number and location to the plurality of first sealing rings;
depositing a solder layer on either each of the plurality of first sealing rings or each of the plurality of second sealing rings;
aligning the device wafer and the lid wafer such that each of the plurality of first sealing rings aligns with the corresponding one of the plurality of second sealing rings leaving a gap between the device wafer and the lid wafer; and
mating the device wafer with the lid wafer in a vacuum environment to form a plurality of vacuum packages, each vacuum package enclosing one or more of the plurality of integrated circuit devices. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A method for vacuum packaging integrated circuit devices, comprising:
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forming on a device wafer a plurality of integrated circuit devices;
forming a plurality of first sealing rings, each of the plurality of first sealing rings surrounding one or more integrated circuit devices, each first sealing ring positioned between the perimeter of the one or more integrated circuit device and one or more bonding pads coupled to each of the one or more integrated circuit devices;
forming on a lid wafer a plurality of second sealing rings corresponding in number and location to the plurality of first sealing rings;
forming a solder layer on either each of the plurality of first sealing rings or each of the plurality of second sealing rings;
aligning the device wafer and the lid wafer such that each of the plurality of first sealing rings aligns with the corresponding one of the plurality of second sealing rings leaving a gap between the device wafer and the lid wafer; and
mating the device wafer with the lid wafer in a vacuum environment to form a plurality of vacuum packages, each vacuum package enclosing one or more of the plurality of integrated circuit devices. - View Dependent Claims (20, 21, 22, 23)
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24. A vacuum package containing one or more integrated circuit devices, comprising:
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one or more integrated circuit devices formed on device wafer, said devices having one or more associated bonding pads;
a sealing ring formed on the device wafer between the perimeter of the one or more integrated circuit devices and the one or more bonding pads coupled to the one or more integrated circuit devices; and
a vacuum package lid sealed to the sealing ring, the vacuum package lid providing a vacuum cell for the one or more integrated circuit devices. - View Dependent Claims (25, 26)
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27. A vacuum package for integrated circuit devices, comprising:
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a sealing ring having one or more spacers, the sealing ring in a designated area on a substrate material, the sealing ring surrounding one or more integrated circuit devices; and
a sealing layer on the sealing ring. - View Dependent Claims (28, 29, 30, 31, 32)
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Specification