SEMICONDUCTOR DEVICE CONDUCTIVE BUMP AND INTERCONNECT BARRIER

• US 20020000665A1
• Filed: 04/05/1999
• Published: 01/03/2002
• Est. Priority Date: 04/05/1999
• Status: Abandoned Application

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: VENKATRAMAN, RAMNATH, VENKATESAN, SURESH, BARR, ALEXANDER L., ADETUTU, OLUBUNMI, GREER, STUART E., REBER, DOUGLAS M., CROWN, STEPHEN R., COLE, REBECCA G., ANTHONY, BRIAN G., BRAECKELMANN, GREGOR, CLEGG, DAVID B.
• Application Number:
  US09/285,666
• Publication Number:
  US 20020000665A1
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/03009 for protecting parts during manufacture
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05157 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05172 : Vanadium [V] as principal constituent
• CPC Class Codes: H01L 2224/0518 : Molybdenum [Mo] as principal constituent
• CPC Class Codes: H01L 2224/05181 : Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05186 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05572 : the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 23/53233 : Copper alloys
• CPC Class Codes: H01L 23/53238 : Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01016 : Sulfur [S]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/0496 : 6th Group
• CPC Class Codes: H01L 2924/0537 : 7th Group
• CPC Class Codes: H01L 2924/0538 : 8th Group
• CPC Class Codes: H01L 2924/0539 : 9th Group
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

Claims

1. A semiconductor device, comprising:

a first interconnect that overlies a semiconductor device substrate;

a insulating barrier layer that overlies the first interconnect;

a second interconnect that overlies portions of the first interconnect and the insulating barrier layer;

a conductive barrier layer that overlies a portion the second interconnect, the conductive barrier layer extending beyond an edge region of the portion of the second interconnect; and

a passivation layer that overlies the conductive barrier layer, the passivation layer having an opening that exposes portions of the conductive barrier layer.

2. The semiconductor device of claim 1, wherein the second interconnect includes mostly copper.

3. The semiconductor device of claim 1, wherein the conductive barrier layer includes a refractory metal nitride.

4. The semiconductor device of claim 1, wherein the conductive barrier layer includes a material selected from a group consisting of titanium, tantalum, tungsten, iridium, and nickel.

5. The semiconductor device of claim 1, further comprising an oxidation-resistant layer that overlies the conductive barrier layer.

6. The semiconductor device of claim 5, wherein the oxidation-resistant layer includes nitrogen.

7. The semiconductor device of claim 5, wherein the oxidation-resistant layer is a silicon layer.

8. The semiconductor device of claim 1, wherein the portion of the second interconnect is further characterized as a bond pad.

9. The semiconductor device of claim 8, wherein a portion of the conductive barrier layer is a laser-alterable connection between at least two conductive regions.

10. The semiconductor device of claim 8, further comprising

a conductive bump that overlies the bond pad.

11. A semiconductor device, comprising:

an interconnect over a semiconductor device substrate;

a passivation layer that overlies the interconnect, the passivation layer having an opening that exposes a portion of the interconnect; and

a conductive barrier layer within the opening that overlies the portion of the interconnect.

12. The semiconductor device of claim 11, wherein the conductive barrier layer covers a sidewall portion of the opening.

13. The semiconductor device of claim 12, wherein the conductive barrier layer extends over a surface portion of the passivation layer adjacent the sidewall portion.

14. The semiconductor device of claim 11, wherein the interconnect includes mostly copper.

15. The semiconductor device of claim 11, wherein the conductive barrier layer includes a refractory metal nitride.

16. The semiconductor device of claim 11, wherein the conductive barrier layer includes a material selected from a group consisting of tantalum, titanium, tungsten, iridium, and nickel.

17. The semiconductor device of claim 11, further comprising forming an oxidation-resistant layer over the conductive barrier layer.

18. The semiconductor device of claim 17, wherein the oxidation-resistant layer includes nitrogen.

19. The semiconductor device of claim 17, wherein the oxidation-resistant layer is a silicon layer.

20. The semiconductor device of claim 11, further comprising a conductive bump over the conductive barrier layer.

21. A method of forming a semiconductor device comprising:

forming a first interconnect overlying a semiconductor device substrate;

forming an insulating barrier layer overlying the first interconnect;

forming a second interconnect overlying portions of the first interconnect and the insulating barrier layer;

forming a conductive barrier layer overlying a portion of the second interconnect, the conductive barrier layer extending beyond an edge region of the portion of the second interconnect;

forming a passivation layer overlying the conductive barrier layer; and

forming an opening in the passivation layer, wherein the opening exposes portions of the conductive barrier layer.

22. The method of claim 21, further comprising forming an oxidation-resistant layer overlying conductive barrier layer.

23. The method of claim 22, wherein the oxidation-resistant layer includes a material selected from a group consisting of nitrogen and silicon.

24. The method of claim 21, wherein a portion of the conductive barrier layer forms a laser-alterable connection between at least two conductive regions.

25. The method of claim 21, wherein forming an opening in the passivation layer further comprises:

forming a partial opening in the passivation layer, wherein a depth of the partial opening is less than a thickness of the passivation layer in a region of the passivation layer where the partial opening is formed;

forming a die coat layer over the passivation layer;

forming an opening in the die coat layer, wherein forming the opening in the die coat layer exposes the partial opening in the passivation layer; and

etching the partial opening in the passivation layer to expose an underlying layer after forming an opening in the die coat layer.

26. The method of claim 21, further comprising:

removing a portion of the conductive barrier layer after forming an opening in the passivation layer, wherein the portion of the conductive barrier layer has a depth; and

forming a conductive bump over the conductive barrier layer after removing a portion of the conductive barrier layer.

27. The method of claim 26, wherein the depth is in a range of approximately 20-40 nanometers.

28. A method of forming a semiconductor device, comprising:

forming an interconnect over a semiconductor device substrate;

forming a passivation layer over the interconnect;

forming an opening in the passivation layer, the opening exposing portions of the interconnect; and

forming a conductive barrier layer within the opening, the conductive barrier layer overlying exposed portions of the interconnect.

29. The method of claim 28, further comprising forming an oxidation-resistant layer over the conductive barrier layer, wherein the oxidation-resistant layer includes a material selected from a group consisting of nitrogen and silicon.

30. The method of claim 28, wherein the conductive barrier layer covers a sidewall portion of the opening and extends over a surface portion of the passivation layer adjacent the sidewall portion.

31. The method of claim 28, wherein the interconnect includes copper.