Modulation circuit and image display using the same

• US 20020000982A1
• Filed: 04/30/2001
• Published: 01/03/2002
• Est. Priority Date: 05/01/2000
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Takagi, Yuichi
• Granted Patent: US 6,771,281 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/02 Addressing, scanning or driving the display screen or processing steps related thereto
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2085 Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

A modulation circuit for outputting a pulse signal modulated in accordance with the value of input data by a predetermined period, comprising a clock generation circuit for generating and outputting a first clock pulse changing in frequency by the predetermined period, a clock counting circuit for receiving the first clock pulse, counting the first clock pulse from a predetermined initial value in an initial stage of the predetermined period, and outputting a clock count and a pulse signal output circuit for comparing magnitudes of the clock count and the value of the input data and inverting a level of the pulse signal in the vicinity of a time when the magnitudes of the clock count and the value of the input data invert.

Claims

1. A modulation circuit for outputting a pulse signal modulated in accordance with the value of input data by a predetermined period, comprising:

a clock generation circuit for generating and outputting a first clock pulse changing in frequency by said predetermined period,

a clock counting circuit for receiving said first clock pulse, counting said first clock pulse from a predetermined initial value in an initial stage of said predetermined period, and outputting a clock count and

a pulse signal output circuit for comparing magnitudes of said clock count and the value of said input data and inverting a level of said pulse signal in the vicinity of a time when the magnitudes of said clock count and the value of said input data invert.

2. A modulation circuit as set forth in claim 1, wherein said clock pulse generation circuit includes

a frequency division setting circuit for outputting a frequency division setting changing in value by said predetermined period and

a prescaler for receiving a second clock pulse and said frequency division setting, dividing said second clock pulse by a frequency division number in accordance with said frequency division setting, and outputting said first clock pulse.

3. A modulation circuit as set forth in claim 1, wherein said clock pulse generation circuit includes

a frequency division setting circuit for outputting a frequency division setting changing in value by said predetermined period;

a prescaler for receiving said first clock pulse and said frequency division setting, dividing said first clock pulse by a frequency division number in accordance with said frequency division setting, and outputting a feedback signal;

a phase comparison circuit for detecting a phase difference between a second clock pulse and said feedback signal and outputting a phase difference signal in accordance with the related phase difference; and

an oscillation circuit for outputting said first clock pulse having a period in accordance with a level of said phase difference signal.

4. A modulation circuit as set forth in claim 1, wherein said clock pulse generation circuit includes

a variable clock period circuit for outputting a variable clock period signal changing in level by the predetermined period and

an oscillation circuit for outputting said first clock pulse having a period in accordance with a level of said variable clock period signal.

5. A modulation circuit as set forth in claim 4, wherein said clock pulse generation circuit includes

a frequency division circuit for dividing said first clock pulse by the predetermined frequency division number and outputting a frequency divided signal and

a phase comparison circuit for detecting a phase difference between a pulse period signal having said predetermined period and said frequency divided signal and outputting a phase difference signal of a level in accordance with the related phase difference and

the oscillation circuit outputs said first clock pulse having a period in accordance with a sum of levels of said variable clock period signal and said phase difference signals.

6. A modulation circuit for outputting a pulse signal modulated in accordance with a value of input data by a predetermined period comprising:

a clock generation circuit for generating and outputting a first clock pulse having a frequency in accordance with the value of said input data;

a clock counting circuit for receiving said first clock pulse, counting said first clock pulse from a predetermined initial value in an initial stage of said predetermined period, and outputting a clock count; and

a pulse signal output circuit for comparing magnitudes of said clock count and the value of said input data and inverting a level of said pulse signal in the vicinity of a time when the magnitudes of said clock count and the value of said input data invert.

7. A modulation circuit as set forth in claim 6, wherein said clock pulse generation circuit includes a prescaler for receiving a second clock pulse and a value of said input data, dividing said second clock pulse by a frequency division number in accordance with the value of said input data, and outputting said first clock pulse.

8. A modulation circuit as set forth in claim 6, wherein said clock pulse generation circuit includes

a prescaler for receiving said first clock pulse and said input data, dividing said first clock pulse by a frequency division number in accordance with the value of said input data, and outputting a feedback signal;

a phase comparison circuit for detecting a phase difference between a second clock pulse and said feedback signal and outputting a phase difference signal in accordance with the related phase difference; and

an oscillation circuit for outputting said first clock pulse having a period in accordance with a level of said phase difference signal.

9. An image display having a light emission element receiving a pulse signal modulated in accordance with a value of input data and emitting light with a luminance in accordance with the level of said pulse signal comprising:

a clock generation circuit for generating and outputting a first clock pulse changing in frequency by a predetermined period;

a clock counting circuit for receiving said first clock pulse, counting said first clock pulse from a predetermined initial value in an initial stage of said predetermined period, and outputting a clock count; and

a pulse signal output circuit for comparing magnitudes of said clock count and the value of said input data and inverting a level of said pulse signal in the vicinity of a time when the magnitudes of said clock count and the value of said input data invert.

10. An image display as set forth in claim 9, wherein said clock pulse generation circuit includes

a frequency division setting circuit for outputting a frequency division setting changing in value by said predetermined period and

a prescaler for receiving a second clock pulse and said frequency division setting, dividing said second clock pulse by a frequency division number in accordance with said frequency division setting, and outputting said first clock pulse.

11. An image display as set forth in claim 9, wherein said clock pulse generation circuit includes

a variable clock period circuit for outputting a variable clock period signal changing in level by the predetermined period and

an oscillation circuit for outputting said first clock pulse having a period in accordance with a level of said variable clock period signal.

12. A image display as set forth in claim 11, wherein said clock pulse generation circuit includes

a frequency division circuit for dividing said first clock pulse by the predetermined frequency division number and outputting a frequency divided signal and

a phase comparison circuit for detecting a phase difference between a pulse period signal having said predetermined period and said frequency divided signal and outputting a phase difference signal of a level in accordance with the related phase difference and

the oscillation circuit outputs said first clock pulse having a period in accordance with a sum of levels of said variable clock period signal and said phase difference signals.

13. An image display having a light emission element receiving a pulse signal modulated in accordance with a value of input data and emitting light with a luminance in accordance with the level of said pulse signal comprising:

a clock generation circuit for generating and outputting a first clock pulse having a frequency in accordance with the value of said input data;

a clock counting circuit for receiving said first clock pulse, counting said first clock pulse from a predetermined initial value in an initial stage of said predetermined period, and outputting a clock count; and

a pulse signal output circuit for comparing magnitudes of said clock count and the value of said input data and inverting a level of said pulse signal in the vicinity of a time when the magnitudes of said clock count and the value of said input data invert.

14. An image display as set forth in claim 13, wherein said clock pulse generation circuit includes a prescaler for receiving a second clock pulse and said input data, dividing said second clock pulse by a frequency division number in accordance with the value of said input data, and outputting said first clock pulse.

15. An image display as set forth in claim 13, wherein said clock pulse generation circuit includes

a prescaler for receiving said first clock pulse and said input data, dividing said first clock pulse by a frequency division number in accordance with the value of said input data, and outputting a feedback signal;

a phase comparison circuit for detecting a phase difference between a second clock pulse and said feedback signal and outputting a phase difference signal in accordance with the related phase difference; and

an oscillation circuit for outputting said first clock pulse having a period in accordance with a level of said phase difference signal.