SEMICONDUCTOR PACKAGE HAVING LIGHT SENSITIVE CHIPS

• US 20020001869A1
• Filed: 02/18/1998
• Published: 01/03/2002
• Est. Priority Date: 02/18/1997
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: FJELSTAD, JOSEPH
• Granted Patent: US 6,583,444 B2
• Time in Patent Office: Days
• US Class Current: 438/48
• CPC Class Codes: H01L 21/4832 Etching a temporary substrate after encapsulation process to form leads
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/32257 the layer connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/48475 connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/85051 Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01009 : Fluorine [F]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80

Abstract

A method of making a microelectronic package includes providing a sacrificial layer having a first surface and providing an optoelectronic element having a front face including one or more contacts and a rear surface and securing the rear surface of the optoelectronic element over the first surface of the sacrificial layer. The one or more contacts are then electrically interconnected with one or more conductive pads on the sacrificial layer and a curable and at least partially transparent encapsulant is provided over the first surface of the sacrificial layer so as to encapsulate the optoelectronic element and the conductive pads. The encapsulant is then cured the sacrificial layer is at least partially removed so as to leave said one or more conductive pads on a bottom surface of the encapsulant, the bottom surface of the encapsulant defining the bottom of the package. The optoelectronic element may include a light sensitive chip such as an ultraviolet-erasable programmable read-only memory (UV EPROM) or a light emitting chip, such as a light emitting diode (LED).

Claims

1. A method of making a microelectronic package comprising the steps of:

providing a sacrificial layer having a first surface and one or more conductive pad areas;

providing an optoelectronic element having a front face including one or more contacts and a rear surface and disposing said rear surface of said optoelectronic element over said first surface of said sacrificial layer;

electrically interconnecting said one or more contacts and said one or more conductive pad areas;

providing a curable and at least partially transparent encapsulant over the first surface of said sacrificial layer so as to encapsulate said optoelectronic element and said one or more conductive pad areas;

curing said encapsulant; and

at least partially removing said sacrificial layer so as to form one or more conductive pads from said one or more conductive pad areas on a bottom surface of said encapsulant, the bottom surface of said encapsulant defining the bottom of said package.

2. The method as claimed in claim 1, the rear surface of said optoelectronic element being exposed at the bottom of said package after the removing said sacrificial layer step.

3. The method as claimed in claim 1, the providing an optoelectronic element step including providing a base having a top surface over said sacrificial layer.

4. The method as claimed in claim 3, the disposing step including attaching the rear surface of said optoelectronic element to the top surface of said base.

5. The method as claimed in claim 4, the attaching step including the step of applying an adhesive over the top surface of said base and abutting the rear surface of said optoelectronic element against said adhesive.

6. The method as claimed in claim 5, wherein said adhesive includes a thermally conductive adhesive.

7. The method as claimed in claim 4, wherein said base includes a conductive base having conductive material.

8. The method as claimed in claim 7, wherein said conductive base is thermally conductive.

9. The method as claimed in claim 7, wherein said conductive base is electrically conductive.

10. The method as claimed in claim 9, wherein said optoelectronic element is electrically interconnected with said conductive base.

11. The method as claimed in claim 1, wherein said optoelectronic element includes a light sensitive semiconductor chip.

12. The method as claimed in claim 1, wherein said optoelectronic element includes an ultraviolet-erasable programmable read-only memory.

13. The method as claimed in claim 1, wherein said electrically interconnecting step includes wire bonding said one or more contacts to said one or more conductive pads.

14. The method as claimed in claim 1, further comprising the step of:

placing an at least partially transparent lid at a top surface of said encapsulant so that said lid overlies said front face of said optoelectronic element.

15. The method as claimed in claim 14, wherein said lid placing step includes the step of forming said lid integrally with said encapsulant.

16. The method of claim 14, wherein said lid includes a material selected from the group consisting of glass, quartz, and rigid polymeric materials.

17. The method as claimed in claim 14, wherein said lid includes a lens for refracting light.

18. The method as claimed in claim 17, wherein said lens includes a Fresnel type lens.

19. The method as claimed in claim 17, wherein said lid includes a top surface remote from said optoelectronic element, the method further comprising the steps of providing a connector for a light transmitting cable on said top surface of said lid.

20. The method as claimed in claim 1, further comprising the step of providing one or more light focusing elements in said encapsulant for focusing light interacting with said optoelectronic element.

21. The method as claimed in claim 19, wherein said connector is integrally formed with said lid.

22. The method as claimed in claim 19, wherein said connector includes a cavity formed therein for receiving the end of said light transmitting cable.

23. The method as claimed in claim 17, wherein said optoelectronic element includes an optical area on the front face thereof, said method further comprising the step of focusing light through said lens and onto said optical area.

24. The method as claimed in claim 1, wherein a plurality of said microelectronic packages are simultaneously manufactured using the same sacrificial layer, the method further comprising the step of separating at least some of said microelectronic packages.

25. The method as claimed in claim 24, wherein the separating step provides a plurality of individual microelectronic packages.

26. The method as claimed in claim 24, wherein the separating step provides a plurality of modules, each said module including at least two optoelectronic elements.

27. The method of claim 1, wherein said encapsulant is transparent to only certain wavelengths of light.

28. A method of making a microelectronic package comprising the steps of:

providing an electrically conductive sheet;

forming a conductive base having a cavity formed therein and at least one conductive pad adjacent said conductive base, said cavity having a light reflective surface;

providing an optoelectronic element having a front face including at least one contact and a rear surface having at least one contact;

attaching said rear surface of said optoelectronic element to said cavity so as to position the optoelectronic element in said cavity and electrically interconnect said optoelectronic element and said conductive base;

electrically interconnecting said front contact of said optoelectronic element and said at least one conductive pad;

providing a curable and at least partially transparent encapsulant over said conductive sheet so as to encapsulate said at least one conductive pad, said conductive base and said optoelectronic element and curing said encapsulant;

selectively removing portions of said conductive sheet so as to electrically isolate said conductive base from said at least one conductive pad.

29. The method as claimed in claim 28, wherein said conductive base and said at least one conductive pad are accessible at a bottom surface of said encapsulant.

30. The method as claimed in claim 28, wherein said cavity includes a bottom and side walls extending therefrom.

31. The method as claimed in claim 28, further comprising the step of covering said cavity with an electrically conductive layer before the attaching step.

32. The method as claimed in claim 28, wherein said electrically conductive layer includes a non-oxidizing material.

33. The method as claimed in claim 28, wherein the forming a conductive base step and the selectively removing step includes selectively etching said conductive sheet.

34. The method as claimed in claim 28, wherein the forming a conductive base step includes stamping said conductive sheet.

35. The method as claimed in claim 28, wherein a plurality of microelectronic packages are manufactured simultaneously using the same conductive sheet, the method further comprising the step of separating at least some of the packages after the selectively removing additional portions step.

36. The method as claimed in claim 35, wherein the separating step provides a plurality of individual packages.

37. The method as claimed in claim 35, wherein the separating step provides a plurality of chip modules, each said module including at least two optoelectronic elements.

38. The method as claimed in claim 28, wherein said optoelectronic element includes a light emitting semiconductor chip.

39. A method of making a multichip module comprising the steps of:

providing a substrate including a dielectric layer disposed between a top conductive layer and a bottom conductive layer;

selectively removing portions of said bottom conductive layer to form an array of conductive pads;

selectively removing portions of said top conductive layer and said dielectric layer to form an array of openings extending through said top conductive layer and said dielectric layer, said array of openings being in alignment with said conductive pads;

providing a plurality of optoelectronic elements over said top conductive layer;

electrically interconnecting said plurality of optoelectronic elements and said top conductive layer;

electrically interconnecting each said optoelectronic element to one of said conductive pads;

providing a curable and at least partially transparent encapsulant over said top conductive layer and said plurality of optoelectronic elements; and

curing said encapsulant.

40. The method as claimed in claim 39, wherein each said optoelectronic element includes a front face having a contact and a rear surface having a contact, the providing step including attaching the rear surfaces of said optoelectronic elements to said top conductive layer.

41. The method as claimed in claim 40, the attaching step including applying an electrically conductive adhesive over said top conductive layer and abutting said rear surfaces of said optoelectronic elements against said electrically conductive adhesive.

42. The method as claimed in claim 40, wherein the electrically interconnecting each said optoelectronic element to one of said conductive pads step includes using flexible conductive elements to interconnect said optoelectronic elements and said conductive pads.

43. A microelectronic package comprising:

an optoelectronic element having a front face including one or more contacts and a rear surface;

flexible conductive leads having first ends connected to said one or more contacts and second ends connected to one or more conductive pads adjacent said optoelectronic element;

an at least partially transparent encapsulant covering said optoelectronic element, said flexible leads and said one or more conductive pads, said one or more conductive pads being exposed on a bottom surface of said encapsulant, the bottom surface of said encapsulant defining the bottom of said package.

44. The package as claimed in claim 43, wherein the rear surface of said base is exposed at the bottom of said package.

45. The package as claimed in claim 43 further comprising a base attached to the rear surface of said optoelectronic element, said base being exposed on the bottom surface of said encapsulant.

46. The package as claimed in claim 43, said package further comprising an at least partially transparent lid over the top surface of said encapsulant and the front surface of said optoelectronic element.

47. The package as claimed in claim 43, wherein said optoelectronic element is selected from the group consisting of light sensitive semiconductor chips and light emitting semiconductor chips.

48. The package as claimed in claim 47, wherein said light sensitive semiconductor chip includes an ultraviolet-erasable programmable read-only memory.

49. The package as claimed in claim 43, wherein said package includes two or more of said optoelectronic elements.

50. The package as claimed in claim 46, wherein said lid includes a material selected from the group consisting of glass, quartz, and rigid polymeric materials.

51. The package as claimed in claim 46, wherein said lid includes a lens for focusing light.

52. The package as claimed in claim 43, wherein said encapsulant has different levels of transparency.

53. The package as claimed in claim 43, wherein said encapsulant includes a color tinted portion.

54. The package as claimed in claim 52, wherein said encapsulant is more transparent in one portion of said package and less transparent in another portion of said package.

55. The method as claimed in claim 43, wherein said encapsulant includes a compliant material.

56. The method of claim 55, wherein the compliancy of said encapsulant varies throughout said package.

57. The method as claimed in claim 55, wherein said encapsulant adjacent said conductive pads is less compliant than said encapsulant adjacent said contacts on said optoelectronic element.

58. A microelectronic package comprising:

an electrically conductive base having a cavity formed in a top surface thereof;

a conductive pad adjacent said conductive base;

an optoelectronic element disposed in said cavity, said optoelectronic element having a front face including a first contact and a rear surface including a second contact, said second contact being electrically connected to said conductive base;

a flexible lead having a first end connected to said first contact and a second end connected to said conductive pad;

an at least partially transparent encapsulant covering said optoelectronic element, said base, said lead and said conductive pad, said conductive base and said conductive pad being exposed on a bottom surface of said encapsulant, the bottom surface of said encapsulant defining the bottom of said package.

59. A package as claimed in claim 58, said cavity including a bottom and side walls extending therefrom and said optoelectronic element having an optical area for emitting light, wherein the side walls of said cavity reflect light transmitted to or from said optical area.

60. The package as claimed in claim 58, said package further comprising an at least partially transparent lid over a top surface of said encapsulant and overlying the front face of said optoelectronic element.

61. The package as claimed in claim 58, wherein said lid includes a material selected from the group consisting of glass, quartz, and rigid polymeric materials.

62. The package as claimed in claim 60, wherein said lid includes a lens for focusing light.

63. The package as claimed in claim 58, wherein said package includes two or more optoelectronic elements.