Method and apparatus for supporting heterogeneous memory in computer systems

• US 20020002662A1
• Filed: 07/10/2001
• Published: 01/03/2002
• Est. Priority Date: 07/13/1998
• Status: Active Grant

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Koenen, David J., Heng, Chai S., Olarig, Sompong Paul
• Granted Patent: US 6,530,007 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

A memory controller capable of supporting heterogeneous memory configurations enables seamless communications between a bus and memory modules having different characteristics. Thus, owners of computer systems need no longer replace entire memory arrays to take advantage of new memory modules; some memory modules may be upgraded to a new type while other memory modules of an older type remain. The memory controller receives memory requests from multiple processors and bus masters, identifies a memory module and memory access parameters for each request, accesses the memory and returns the resulting data (during a read request) or stores the data (during a write request). In some systems, the memory controller of the present invention is a two-tier memory controller system having a first memory controller coupled to the bus and to the second tier of memory controllers or RAM personality modules that translate between the first memory controller and a particular type of memory module. Typically, between the tiers a protocol is used which is representative of a typical clocked synchronous dynamic random access memory (SDRAM), although another protocol could be used. From the perspective of the processor bus or host bus coupled to the front end of the first memory controller, the entire memory controller system behaves as a single memory controller. From the perspective of memory, the back end of the RAM personality module is seen as a memory controller designed specifically to be configured for that memory type. Consequently, although the front end of the RAM personality module can be standardized across the system, compatible with the back end of the first memory controller, and in most embodiments of the present invention, the back end of the RAM personality module differs among the controller modules in the second tier, according to the variety of the memory modules in the memory system.

Claims

1. A computer system comprising:

at least one bus, the bus having address, data, and control signals;

at least one processor for processing data, for controlling operations of the bus and for performing read and write operations;

a memory controller system, coupled to the bus;

a heterogeneous main memory array, having a first memory unit and a second memory unit, the first and second memory units having different access parameters.

2. The computer system of claim 1, wherein:

the memory controller includes a first device coupled to the bus, coupled to receive write operations and read operations from the bus, and receive data corresponding to a write operation and to provide data corresponding to all read operations via said bus;

a second memory controller component, coupled to the first memory controller component and to at least one memory module of a first type, the second memory controller module translating memory access requests from the first memory controller module to the memory and further translating any response from the memory module to the first memory controller component;

a third memory controller component, coupled to the first memory controller component in parallel with the second memory controller component, the third memory controller component further coupled to a memory module of the second type, the third memory controller component translating memory access requests from the first memory controller component to the second memory module, and further translating any response from the second memory module to the first memory controller component.

3. The computer system of claim 2, wherein the first memory module has no fast page mode, and wherein the second memory module has a fast page mode.

4. The computer system of claim 1, wherein the memory controller comprises:

a first memory controller component, coupled to exchange memory access requests, control information, data, and addresses, and bus master indexes, with a bus;

a first memory controller component having a first type, the first memory component being coupled to the first memory controller component

a second memory controller component, coupled to the first memory controller component; and

a second memory component of a different type from the first memory component, coupled to the second memory controller component, such that the second memory controller component translates memory address, data, control, and index information between the first memory controller component and the second memory component, wherein no translation is necessary between the first memory controller component and the first memory component.

5. The memory controller of claim 1, further comprising:

a peripheral component interconnect (PCI) bus, coupled to the memory controller, the PCI bus having address, data, control, and index signals; and

a bus master coupled to the PCI bus for controlling operations of the PCI bus and performing read and write operations via the memory controller to the first and second memory components.

6. The memory controller of claim 1, the memory controller further comprising:

a first set of signals coupled to the bus, for receiving address signals from the bus;

a command signal, coupled to the bus, for receiving commands;

a data signal, coupled to the bus, for transferring data;

a clock signal, coupled to the bus, for receiving a synchronizing clock signal; and

a serial presence detect input, coupled to bus, for exchanging information identifying memory modules to the bus;

a second set of memory address signals, for exchanging address information with another component;

a row address strobe (RAS) signal for indicating that an address in the second set of memory addresses is a row address;

a column address strobe signal (CAS), for indicating that the memory address in the second set of memory addresses is a column address;

a write enable (WE) signal, for allowing data in a memory module to be altered;

a set of data signals, for exchanging data with another component; and

an I₂C set of signals, for exchanging serial presence detect information with the other component.

7. The memory controller of claim 1, wherein the first type of memory component is selected from a group consisting of direct-Rambus, SynchLink, SLDRAM, fast page, Extended Data Out (EDO), double data rate (DDR) synchronous DRAM, or any memory module with SPD or PPD.

8. The computer system of claim 1, further comprising a data strobe from the memory component to the memory controller, for indicating the availability of data within the memory component.

9. The computer system of claim 1, further comprising a posting element, for storing multiple write operations.

10. The computer system of claim 1, further comprising a phase lock loop, the phase lock loop enabling the second tier to synchronize to the first tier.

12. The computer system of claim 1, wherein the first controlling means further comprises:

a first portion coupled to receive write operations and read operations from the first bus means, and receive response data corresponding to a write operation and to provide the response data via said first bus means;

a second portion, coupled between the first portion and at least one storing means of the first type, the second portion translating memory access requests from the first portion to the access parameters of the first storing means and further translating any response from the storing means to the first portion;

a third portion, coupled between the first portion and at least one storing means of the second type, the third portion being in parallel with the second portion, the third portion translating memory access requests from the first portion to the access parameters of the second storing means, and further translating any response from the second storing means to the first portion.

13. The computer system of claim 12, wherein the first storing means has no fast page mode, and wherein the second storing means has a fast page mode.

11. A computer system comprising:

a first bus means for transferring address, data, and control signals;

at least one means for processing data, for controlling operations of the first bus means and for performing read and write operations;

a first means of a first type for storing data, the first storing means having a first set of access parameters;

a second means of a second type for storing data, the second storing means having a second set of access parameters different from the first set;

a first controlling means for selecting one of the storing means and for transferring address, data, and control signals between the first transferring means and the selected storing means.

14. The computer system of claim 11, wherein the first controlling means comprises:

a first portion, coupled to transfer memory access requests, control information, data, and addresses, bus master indexes, and responses thereto between the first bus means and the first storing means according to the first set of access parameters;

a second portion, coupled to transfer memory access requests, control information, data, and addresses, bus master indexes, and responses thereto between the first portion and the second storing means according to the second set of access parameters.

15. The computer system of claim 11, further comprising:

a second bus means, coupled to the first controlling means, for transferring address, data, control, and index signals; and

a bus master coupled to the second bus for controlling operations of the second bus means and performing read and write operations via the first controlling means to the first and second storing means.

16. The computer system of claim 11, the first controller means further comprising:

receiving means for receiving address signals from the first bus means;

a command signaling means, coupled to the first bus means, for receiving commands;

a clock signaling means, coupled to the first bus means, for receiving a synchronizing clock signal; and

a serial presence detect input, coupled to first bus means, for exchanging information identifying memory modules to the first bus means;

a second set of memory address signaling means, for exchanging address information with another component;

a row address strobe (RAS) signaling means for indicating that an address in the second set of memory addresses is a row address;

a column address strobe signaling means (CAS), for indicating that the memory address in the second set of memory addresses is a column address;

a write enable (WE) signaling means, for allowing data in a memory module to be altered;

a set of data signaling means, for exchanging data with another component;

and

an I²C set of signaling means, for exchanging serial presence detect information with the other component.

17. The first controlling means of claim 11, wherein the first type of storing means is selected from a group consisting of direct-Rambus, SynchLink, SLDRAM, or double data rate (DDR) synchronous DRAM or any future DRAMs with SPD.

18. The computer system of claim 11, further comprising a data strobe from the storing means to the first controlling means, for indicating the availability of data within the storing means.

19. The computer system of claim 11, further comprising a posting element, for storing multiple write commands.

20. The computer system of claim 11, further comprising a phase lock loop, the phase lock loop enabling the second tier to synchronize to the first tier.

21. In a computer system having at least a first bus, the bus having address, data, and control signals, at least one processor for processing data, for controlling operations of the bus and for performing read and write operations, and a heterogeneous main memory array, having a first memory unit and a second memory unit, the first and second memory units having different access parameters, a memory controller system coupled to the bus, the memory controller system comprising:

a first portion configured to be coupled to receive write operations and read operations from the first bus, and receive response data corresponding to a write operation and to provide the response data via said first bus;

a second portion, coupled to the first portion and further configured to be coupled to at least one memory module of the first type, the second portion for translating memory access requests from the first portion to the first memory module according to the access parameters of the first memory module and further for translating any response from the memory module to the first portion;

a third portion, coupled to the first portion and further configured to be coupled to at least one memory module of the second type, the third portion being in parallel with the second portion, the third portion for translating memory access requests from the first portion to the second memory module according to the access parameters of the second memory module and further for translating any response from the second memory module to the first portion.

22. The memory controller system of claim 21, wherein the first portion is configured to be coupled to a memory module has no fast page mode, and wherein the second portion is configured to be coupled to a second memory module has a fast page mode.

24. The memory controller of claim 21, further comprising:

a connector configured to exchange address, data, control, and index signals corresponding to read and write operations and response data thereto with a bus master, via a second bus.

25. The memory controller of claim 24, wherein:

the second bus is peripheral component interconnect (PCI) bus, the memory controller configured to be coupled thereto, such that the memory controller enables a bus master on the PCI bus to control operations of the second bus and to perform read and write operations via the memory controller to the first and second memory units.

26. The memory controller of claim 21, wherein:

the memory controller is further configured to exchange with a bus;

a first set of address signals, for receiving address signals from the bus;

a command signal, for receiving commands;

a data query signal, for indicating data requests;

a clock signal, for receiving a synchronizing clock signal; and

a serial presence detect input, for exchanging information identifying memory modules to the bus;

and wherein the memory controller is further configured to exchange with another component;

a second set of memory address signals, for exchanging address information;

a row address strobe (RAS) signal for indicating that an address in the second set of memory addresses is a row address;

a column address strobe signal (CAS), for indicating that the memory address in the second set of memory addresses is a column address;

a write enable (WE) signal, for allowing data in a memory module to be altered;

a set of data signals, for exchanging data with another component; and

an I²C set of signals, for exchanging serial presence detect information with the other component.

27. The memory controller of claim 21, wherein:

at least one of the first and second portions is configured to be coupled to a memory unit selected from a group consisting of direct-Rambus, SynchLink, SLDRAM, or double data rate (DDR) synchronous DRAM.

28. The memory controller system of claim 21, further configured to receive a data strobe from the memory component to the memory controller, the data strobe for indicating the availability of data within the memory unit.

29. The memory controller system of claim 21, further comprising a posting element, for memory module multiple write commands.

30. The memory controller system of claim 21, further comprising a phase lock loop, the phase lock loop enabling the second tier to synchronize to the first tier.

23. In a computer system having at least a first bus, the bus having address, data, and control signals, at least one processor for processing data, for controlling operations of the bus and for performing read and write operations, and a heterogeneous main memory array, having a first memory unit and a second memory unit, the first and second memory units having different access parameters, a memory controller system coupled to the bus, the memory controller system comprising:

a first portion, configured to be coupled to transfer memory access requests, control information, data, and addresses, bus master indexes, and responses thereto between the bus and the first memory unit according to the first set of access parameters;

a second portion, coupled to transfer memory access requests, control information, data, and addresses, bus master indexes, and responses thereto between the first portion and the second memory unit according to the second set of access parameters.

31. In a computer system having a first bus for transferring address, data, and control signals, at least one for processing data, for controlling operations of the first bus and for performing read and write operations, and a memory controller, a heterogeneous memory array, the heterogeneous memory array comprising:

means for connecting to a memory bus;

a first memory module of a first type for storing data, the first memory module having a first set of access parameters;

a second memory module of a second type for storing data, the second memory module coupled to said means and having a second set of access parameters different from the first set;

a first personality module coupled between said connecting means and said second memory module, the personality module configured to translate memory access signals from the connecting means to the second memory module and from the second memory module to the connecting means.

32. The memory array of claim 31, wherein exactly one of the first memory module and the second memory module has a fast page mode.

33. The memory array of claim 31, wherein the first type of memory module is selected from a group consisting of direct-Rambus, SynchLink, SLDRAM, or double data rate (DDR) synchronous DRAM.

34. The memory array of claim 31, further comprising a data strobe generator for generating a data strobe for indicating the availability of data within the memory module.

35. The memory array of claim 31, wherein at least one of the memory modules is a synchronous device, the memory array further comprising a phase lock loop for synchronizing the synchronous memory module.

40. The memory array of claim 31, wherein the memory module is a synchronous device, the memory card further comprising a phase lock loop for synchronizing the synchronous memory module.

36. For connection to a computer system having a first bus for transferring address, data, and control signals, at least one for processing data, for controlling operations of the first bus and for performing read and write operations, and a memory controller, a memory card, the memory card comprising:

means for connecting to a memory bus;

a first memory module of a first type for storing data, the first memory module having a first set of access parameters; and

a first personality module coupled between said connecting means and said second memory module, the personality module configured to translate memory access signals from the connecting means to the second memory module and from the second memory module to the connecting means.

37. The memory card of claim 36, wherein the first memory module has a fast page mode.

38. The memory card of claim 36, wherein the first type of memory module is selected from a group consisting of direct-Rambus, SynchLink, SLDRAM, or double data rate (DDR) synchronous DRAM.

39. The memory card of claim 36, further comprising a data strobe generator for generating a data strobe for indicating the availability of data within the memory module.

41. In a computer system having a first bus for transferring address, data, and control signals, at least one for processing data, for controlling operations of the first bus and for performing read and write operations, a memory controller for selecting memory modules and for transferring address, data, and control signals between the bus and the selected memory module, and a heterogeneous memory array having a plurality of memory modules coupled to the memory controller, a method for exchanging data between the bus and the selected memory module, the method comprising the steps of:

receiving a memory access request from the memory controller, the memory access request being compatible with a first set of access parameters;

based on the memory access request, selecting a memory module;

when the selected memory module is configured to be accessed according to access parameters compatible with the memory controller, providing the memory access request to the selected memory module;

when the selected memory module is not configured to be accessed according to access parameters compatible with the memory controller, performing the steps of;

providing the memory access request to a personality module compatible with the selected memory module, the personality module being configured between the memory controller and the selected memory module;

translating the memory access request to a second set of access parameters compatible with the selected memory module; and

providing the translated memory access request to the selected memory module; and

when the selected memory module is not configured to be accessed according to access parameters compatible with the memory controller and the access is a read access, performing the steps of;

receiving response data from the selected memory module, according to the second set of access parameters;

translating the response data to the first set of access parameters; and

providing translated response data to the memory controller.

42. The method of claim 41, wherein the step of translating includes a step of modifying a data rate.