Shallow trench isolation type semiconductor device and method of the same

• US 20020003275A1
• Filed: 07/06/2001
• Published: 01/10/2002
• Est. Priority Date: 07/10/2000
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Keum-Joo, Song, Chang-Lyoung, Park, Tai-Su, Hwang, In-Seak, Kwon, Young-min, Moon, Bong-Ho
• Application Number:
  US09/899,224
• Publication Number:
  US 20020003275A1
• Time in Patent Office: Days
• US Class Current: 257/510
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264

Abstract

A shallow trench type (STI) type semiconductor device employs an etch-stop layer pull-pack approach and a liner as an oxygen barrier, enhancing stability of gate insulation and reliability of transistor operation, wherein a trench sidewall thermal oxide layer with a thickness of 20 Å-140 Å is formed between silicon substrate and the liner, controlling the sidewall liner tension that acts on the substrate. This makes it possible to control the thickness of a gate insulating layer adjacent to a trench to a value equal to or greater than a value in the middle of an active region. Further, a corner adjacent to the trench is rounded to increase the voltage handling capability of device.

Claims

1. A shallow trench isolation (STI) type semiconductor device employing a liner as an oxygen barrier, comprising:

a trench sidewall thermal oxide layer formed between the liner and a silicon substrate to a thickness of 20 Å

-140 Å

,

wherein a top of the liner is located at a position where a level difference from the top of the liner to an upper surface of the substrate is 150 Å

or less.

2. The device of claim 1, wherein a thickness of the trench sidewall oxide layer is 50 Å

-100 Å

.

3. The device of claim 1, wherein a thickness of a gate insulating layer adjacent to the trench is identical to or greater than that of a gate insulating layer in the middle of an active region.

4. A method of forming a shallow trench isolation (STI) type semiconductor device, comprising:

etching a substrate where a pattern of an etch-stop layer covers an active region, forming a trench;

forming a thermal oxide layer on a sidewall of the trench;

isotropically etching the pattern and removing a lateral end of the pattern by a predetermined width, forming a shrunk pattern;

stacking a liner for an oxygen barrier on the thermal oxide layer of the substrate;

stacking a CVD silicon oxide layer on the substrate after the liner is formed, filling the trench;

removing and planarizing the CVD silicon oxide layer over the etch-stop layer;

removing the shrunk pattern; and

forming a gate oxide layer on the active region,

wherein a thickness of the thermal oxide layer on the sidewall of the trench is controlled to be 20 Å

-140 Å

during the stacking of the liner.

5. The method of claim 4, wherein the thickness of the thermal oxide layer is controlled to be 50 Å

-100 Å

.

6. The method of claim 4, wherein the etch-stop layer is made of silicon nitride.

7. The method of claim 4, wherein forming the thermal oxide layer occurs after forming the shrunk pattern.

8. The method of claim 4, wherein controlling the thermal oxide layer within a thickness range of 20 Å

-140 Å

is done by forming the thermal oxide layer of thickness greater than the required thickness range, and etching the thermal oxide layer to reach the thickness range by means of a fluorine (F)-contained etchant.

9. The method of claim 4, wherein the predetermined width in forming the shrunk pattern is 100 Å

-500 Å

.

10. The method of claim 4, wherein the liner comprises a CVD silicon nitride to a thickness of 50 Å

-150 Å

.

11. The method of claim 4, wherein removing the shrunk pattern is achieved by phosphoric acid wet etching.

12. The method of claim 6, wherein removing the shrunk pattern is achieved by wet etching in a mixture of fluorine contained etchant and phosphoric acid.

13. The method of claim 4, wherein the gate oxide layer is formed by a thermal oxidation technique.

14. The method of claim 13, wherein the thickness of the gate oxide layer adjacent to the trench is identical to or greater than that of the gate oxide layer in the middle of the active region.