Semiconductor device and method for fabricating same

• US 20020003293A1
• Filed: 06/29/2001
• Published: 01/10/2002
• Est. Priority Date: 07/04/2000
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kobayashi, Yutaka
• Granted Patent: US 6,806,560 B2
• Time in Patent Office: Days
• US Class Current: 257/676
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48105 Connecting bonding areas at different heights
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H05K 1/111 : Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 2201/10977 : Encapsulated connections
• CPC Class Codes: H05K 2203/0307 : Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites
• CPC Class Codes: H05K 3/305 : Affixing by adhesive
• CPC Class Codes: H05K 3/381 : by special treatment of the substrate
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

Lands and Cu wirings are formed on surfaces of a glass epoxy substrate, and a solder mask is formed on the lands and the Cu wirings to form a chip-mounting substrate. A bottom surface of the chip-mounting substrate is made rough, and a semiconductor chip is mounted on a top surface of the chip-mounting substrate. Through holes communicating with the Cu wirings are formed on the solder mask to expose the Cu wirings. Solder balls are formed on the Cu wrings by thermal compression welding. Underfill material is injected into a clearance formed between the chip mounting substrate and a printed circuit board. Since the surface of the chip-mounting substrate is made rough, an area of a contact surface between the chip-mounting substrate and underfill material increases, hence an adhesive strength between the chip-mounting substrate and the printed circuit board is heightened.

Claims

1. A semiconductor device, comprising:

a semiconductor chip,

a chip-mounting substrate which is provided with said semiconductor chip mounted on a top surface thereof and first conductive pads formed on a bottom surface thereof and connected with said semiconductor chip electrically,

solder balls formed on said first conductive pads,

a printed circuit board on which second conductive pads connected with said solder balls are formed, and

underfill material injected into a clearance formed between said chip-mounting substrate and said printed circuit board,

wherein unevenness is formed on a surface which is brought into contact with said underfill material of at least one of said chip-mounting substrate and said printed circuit board.

2. A semiconductor device according to claim 1, wherein:

said unevenness is formed on said first conductive pads or on said second conductive pads selectively.

3. A semiconductor device according to claim 1, wherein:

said unevenness is shaped into a slit-like configuration or into a dimple-like configuration.

4. A semiconductor device, comprising:

a semiconductor chip,

a lead frame which is provided with said semiconductor chip mounted thereon and electrically connected with said semiconductor chip, and

a printed circuit board including third conductive pads which are formed thereon and brought into contact with said lead frame,

wherein at least one of said lead frame and said printed circuit board is provided with unevennesses at contact surfaces therebetween.

5. A method for fabricating a semiconductor device, comprising the steps of:

forming fourth conductive pads on a bottom surface of a chip-mounting substrate,

forming unevenness on said bottom surface of said chip-mounting substrate,

mounting a semiconductor chip on a top surface of said chip-mounting substrate,

connecting said semiconductor chip with said fourth conductive pads electrically,

forming solder balls on said fourth conductive pads,

assembling said chip-mounting substrate into a printed circuit board by connecting solder balls with fifth conductive pads formed on said printed circuit board, and

injecting underfill material into a clearance formed between said chip-mounting substrate and said printed circuit board.

6. A method for fabricating a semiconductor device according to claim 5, wherein:

said step of forming said unevenness on said bottom surface of said chip-mounting substrate comprises the step of forming unevennesses on said fourth conductive pads selectively.

7. A method for fabricating a semiconductor device, comprising the steps of:

forming sixth conductive pads on a bottom surface of a chip-mounting substrate,

mounting a semiconductor chip on a top surface of said chip-mounting substrate,

connecting said semiconductor chip with said sixth conductive pads electrically,

forming solder balls on said sixth conductive pads,

forming unevenness on a surface of a printed circuit board on which seventh conductive pads are formed,

assembling said chip-mounting substrate into said printed circuit board by connecting said solder balls with said seventh conductive pads formed on said printed circuit board, and

injected underfill material into a clearance formed between said chip-mounting substrate and said printed circuit board.

8. A method for fabricating a semiconductor device according to claim 7, wherein:

said step of forming said unevenness on said surface of said printed circuit board comprises the step of forming unevennesses on said seventh conductive pads selectively.

9. A method for fabricating a semiconductor device, comprising the steps of:

forming eighth conductive pads on a bottom surface of a chip-mounting substrate,

forming a first unevenness on a bottom surface of said chip-mounting substrate,

mounting a semiconductor chip on a top surface of said chip-mounting substrate,

connecting said semiconductor chip with said eighth conductive pads electrically,

forming solder balls on said eighth conductive pads,

forming a second unevenness on a surface of a printed circuit board on which ninth conductive pads are formed,

assembling said chip-mounting substrate into said printed circuit board by connecting said solder balls with said ninth conductive pads, and

injecting underfill material into a clearance formed between said chip-mooting substrate and said printed circuit board.

10. A method for fabricating a semiconductor device according to claim 9, wherein:

said step of forming said first unevenness comprises the step of forming unevennesses on surfaces of said eighth conductive pads selectively, and

said step of forming said second unevenness comprises the step of forming unevennesses on surfaces of said ninth conductive pads selectively.

11. A method for fabricating a semiconductor device, comprising the steps of:

forming unevennesses on predetermined parts of a lead frame,

mounting a semiconductor chip on said lead frame,

connecting said semiconductor chip with said lead frame electrically, and

assembling said lead frame on which said semiconductor chip is mounted into a printed circuit board by bringing said unevennesses formed on said lead frame into contact with tenth conductive pads formed on said printed circuit board.

12. A method for fabricating a semiconductor device, comprising the steps of:

mounting a semiconductor chip on a lead frame,

forming unevennesses on surfaces of eleventh conductive pads formed on a printed circuit board, and

assembling said lead frame on which said semiconductor chip is mounted into said printed circuit board by connecting said lead frame with said eleventh conductive pads on which said unevennesses are formed.

13. A method for fabricating a semiconductor device, comprising the steps of:

forming first unevennesses on predetermined parts of a lead frame,

mounting a semiconductor chip on said lead frame,

connecting said semiconductor chip with said lead frame electrically,

forming second unevennesses on surfaces of twelfth conductive pads formed on a printed circuit board, and

assembling said lead frame on which said semiconductor chip is mounted into said printed circuit board by bringing said first unevennesses formed on said lead frame into contact with said second unevennesses formed on said twelfth conductive pads.