Semiconductor device and method of manufacturing the same

• US 20020004270A1
• Filed: 08/20/2001
• Published: 01/10/2002
• Est. Priority Date: 12/25/1998
• Status: Active Grant

• Current Assignee: Pannova Semic, LLC (Vector Capital Corporation)
• Original Assignee: Masaru Moriwaki, Takayuki Yamada
• Inventors: Yamada, Takayuki, Moriwaki, Masaru
• Granted Patent: US 6,509,225 B2
• Time in Patent Office: Days
• US Class Current: 438/241
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/46 with an inter-gate dielectric layer also being used as part of the peripheral transistor

Abstract

A semiconductor device comprises a first MOSFET and a second MOSFET. The first MOSFET includes a first gate insulating film formed on a semiconductor substrate and having a relatively large thickness and a first gate electrode composed of a polysilicon film formed on the first gate insulating film The second MOSFET includes a second gate insulating film formed on the semiconductor substrate and having a relatively small thickness and a second gate electrode composed of a metal film made of a refractory metal or a compound of a refractory metal and formed on the second gate insulating film.

Claims

1. A method of manufacturing a semiconductor device, the method comprising

a first film forming step of successively forming, on a 20 semiconductor substrate, a first insulating film having a relatively large thickness and a polysilicon film;

a first patterning step of patterning the polysilicon film and the first insulating film to form a first-layer gate insulating film of a flash memory and a dummy gate insulating film, each being composed of the first insulating film, and to form a floating gate electrode of the flash memory and a dummy gate electrode, each being composed of the polysilicon film;

a sidewall forming step of forming sidewalls on each of the floating gate electrode and the dummy gate electrode;

an insulating film removing step of depositing an interlayer insulating film over the entire surface of the semiconductor substrate, removing the portions of the interlayer insulating film overlying the floating gate electrode and the dummy gate electrode, and thereby exposing the floating gate electrode and the dummy gate electrode;

an etching step of forming, on the interlayer insulating film, a second insulating film covering the floating gate electrode and exposing the dummy gate electrode, performing etching by using the second insulating film to remove the dummy gate electrode and

the dummy gate insulating film, and thereby forming a depressed portion internally of the sidewalls of the dummy gate electrode;

a second film forming step of successively forming, over the entire surface of the semiconductor substrate, a third insulating film having a relatively small thickness and a metal film such that the depressed portion is filled therewith; and

a second patterning step of patterning the second insulating film, the third insulating film, and the metal film to form a second-layer gate insulating film of the flash memory composed of the second and third insulating films, a gate insulating film of a FET composed of the third insulating film, a control electrode of the flash memory composed of the metal film, and a gate electrode of the FET composed of the metal film.

2. The method of claim 1, wherein the etching step includes the step of removing the dummy gate electrode and the dummy gate insulating film by wet etching.

3. The method of claim 1, wherein

the first patterning step includes the step of patterning the polysilicon film and the first insulating film to form a capacitor insulating film composed of the first insulating film and a capacitor lower electrode composed of the polysilicon film and

the second patterning step includes the step of patterning the second insulating film, the third insulating film, and the metal film to form a capacitor insulating film composed of the second and third insulating films and a capacitor upper electrode composed of the metal film.

4. A method of manufacturing a semiconductor device, the method comprising:

a first film forming step of successively forming, on a semiconductor substrate, a first insulating film having a relatively large thickness and a multilayer structure being composed of a lower-layer polysilicon film and an upper-layer metal film of a refractory metal or a compound of a refractory metal and

a patterning step of patterning the multilayer structure and the first insulating film to form a first gate insulating film, each being composed of the first insulating film, and to form a first gate electrode of the first FET and a dummy gate electrode, each being composed of the multilayer structure;

a sidewall forming step of forming sidewall on each of the first gate electrode and the dummy gate electrode;

an insulating film removing step of depositing an interlayer insulating film over the entire surface of the semiconductor substrate, removing the portion of the interlayer insulating film overlying the first gate electrode and the dummy gate electrode, and thereby exposing the first gate electrode and the dummy gate electrode;

an etching step of forming, on the interlayer insulating film, a mask pattern covering the first gate electrode and exposing the dummy gate electrode, performing etching by using the mark pattern to remove the dummy gate electrode and the dummy gate insulating film, and thereby forming a depressed portion internally portion internally of the sidewalls of the dummy gate electrode;

a second film forming step of successively forming, over the entire surface of the semiconductor substrate, a second insulating film having a relatively small thickness and a metal film such that the depressed portion is filled therewith; and

a film removing step of removing the mark pattern and the portion of the second insulating film and the metal film located externally of the depressed portion and thereby forming a second gate insulating film and a second FET composed of the second insulating film and a second gate electrode of the second FET composed of the metal film.