Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region

• US 20020004290A1
• Filed: 12/11/2000
• Published: 01/10/2002
• Est. Priority Date: 05/13/1999
• Status: Active Grant

• Current Assignee: Carl J. Radens, Ulrike Gruening
• Original Assignee: Carl J. Radens, Ulrike Gruening
• Inventors: Radens, Carl J., Gruening, Ulrike
• Granted Patent: US 6,399,978 B2
• Time in Patent Office: Days
• US Class Current: 438/484
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap

Abstract

A method and structure for manufacturing an integrated circuit device includes forming a storage device in a substrate, lithographically forming a gate opening in the substrate over the storage device, forming first spacers in the gate opening, forming a strap opening in the substrate using the first spacers to align the strap opening, forming second spacers in the strap opening, forming an isolation opening in the substrate using the second spacers to align the isolation opening, filling the isolation opening with an isolation material, removing the first spacers and a portion of the second spacers to form a step in the gate opening, (wherein the second spacers comprise at least one conductive strap electrically connected to the storage device) forming a first diffusion region in the substrate adjacent the conductive strap, forming a gate insulator layer over the substrate and he step, forming a gate conductor over a portion of the gate insulator layer above the step, forming a second diffusion region in the substrate adjacent the gate conductor and forming a contact over the diffusion region and isolated from the gate conductor, wherein a voltage in the gate conductor forms a conductive region in the substrate adjacent the step and the conductive region electrically connects the strap and the contact.

Claims

1. A method of manufacturing an integrated circuit chip comprising:

forming an opening having at least one step in a substrate;

forming a first conductor in said opening below said step;

forming a first diffusion region in said substrate adjacent said first conductor and below said step;

forming a gate conductor over said step;

forming a second conductor over said substrate adjacent said gate conductor; and

forming a second diffusion region in said substrate adjacent said second conductor.

2. The method in claim 1, wherein said forming of said opening comprises:

lithographically forming a gate opening in said substrate;

forming first spacers in said gate opening;

forming a strap opening in said substrate using said first spacers to align said strap opening;

forming second spacers in said strap opening; and

forming an isolation opening in said substrate using said second spacers to align said isolation opening.

3. The method in claim 2, further comprising filling said isolation opening with an isolation material, wherein said forming of said isolation opening in said substrate and said filling of said isolation opening with an isolation material comprises forming a first portion of an active area isolation region, said method further comprising forming active area stripes to form a second portion of said active area isolation region.

4. The method in claim 2, further comprising removing said first spacers and a portion of said second spacers to form said step in said opening, wherein said second spacers comprise said first conductor.

5. The method in claim 2, wherein said gate opening is wider than said strap opening and said strap opening is wider than said isolation opening.

6. The method in claim 1, wherein a voltage in said gate conductor forms a conductive region in said substrate adjacent said step, said conductive region electrically connecting said first conductor and said second conductor.

7. The method in claim 1, wherein said opening is formed over a deep trench capacitor, said first conductor bisecting a plane of said deep trench capacitor.

8. The method in claim 1, wherein said integrated circuit device comprises a partially vertical transistor, said first conductor comprises a source region and said second conductor comprises a drain region.

9. A method of manufacturing an integrated circuit device comprising:

forming a storage device in a substrate;

lithographically forming a gate opening in said substrate over said storage device;

forming first spacers in said gate opening;

forming a strap opening in said substrate using said first spacers to align said strap opening;

forming second spacers in said strap opening;

forming an isolation opening in said substrate using said second spacers to align said isolation opening;

filling said isolation opening with an isolation material;

removing said first spacers and a portion of said second spacers to form a step in said gate opening, wherein said second spacers comprise at least one conductive strap electrically connected to said storage device;

forming a first diffusion region in said substrate adjacent said conductive strap;

forming a gate insulator layer over said substrate and said step;

forming a gate conductor over a portion of said gate insulator layer above said step;

forming a second diffusion region in said substrate adjacent said gate conductor; and

forming a contact over said diffusion region and isolated from said gate conductor,

wherein a voltage in said gate conductor forms a conductive region in said substrate adjacent said step, said conductive region electrically connecting said strap and said contact.

10. The method in claim 9, wherein said forming of said isolation opening in said substrate and said filling of said isolation opening with said isolation material comprises forming a first portion of an active area isolation region, said method further comprising forming active area stripes to form a second portion of said active area isolation region.

11. The method in claim 9, wherein said forming of said storage device comprises forming a deep trench capacitor, said strap bisecting a plane of said deep trench capacitor.

12. The method in claim 9, wherein said gate opening is wider than said strap opening and said strap opening is wider than said isolation opening.

13. The method in claim 9, wherein said integrated circuit device comprises a partially vertical transistor, said strap comprises a source region and said contact comprises a drain region.

14. An integrated circuit chip comprising:

a substrate;

an opening in said substrate, said opening having at least one step;

a first conductor in said opening below said step;

a first diffusion region in said substrate adjacent said first conductor and below said step;

a gate conductor over said step;

a second conductor over said substrate adjacent said gate conductor; and

a second diffusion region in said substrate adjacent said second conductor.

15. The integrated circuit chip in claim 14, wherein said opening includes:

a lithographically formed gate opening;

a strap opening aligned with said gate opening using first spacers; and

an isolation opening aligned with said strap opening using second spacers.

16. The integrated circuit chip in claim 15, further comprising an isolation material filling said isolation opening, wherein said isolation material comprises a first portion of an active area isolation region, said integrated circuit chip further comprising active area stripes forming a second portion of said active area isolation region.

17. The integrated circuit chip in claim 15, wherein said first spacers and a portion of said second spacers are removed to form said step in said opening, wherein said second spacers comprise said first conductor.

18. The integrated circuit chip in claim 15, wherein said gate opening is wider than said strap opening and said strap opening is wider than said isolation opening.

19. The integrated circuit chip in claim 14, wherein a voltage in said gate conductor forms a conductive region in said substrate adjacent said step, said conductive region electrically connecting said first conductor and said second conductor.

20. The integrated circuit chip in claim 14, wherein said opening is formed over a deep trench capacitor, said first conductor bisecting a plane of said deep trench capacitor.

21. The integrated circuit chip in claim 14, wherein said first conductor comprises a source region, said second conductor comprises a drain region and said integrated circuit chip comprises a partially vertical transistor.