xDSL symbol processor & method of operating same

• US 20020004871A1
• Filed: 03/01/2001
• Published: 01/10/2002
• Est. Priority Date: 03/01/2000
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Liu, Ming-Kang
• Granted Patent: US 6,965,960 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 12/2856 Access arrangements, e.g. Internet access asynchronous transfer mode networks H04L12/5601; broadband local area networks H04L12/2801; optical access or distribution networks H04Q11/0067; access to open networks H04L12/5691; digital subscriber line end-user equipment and bit-level processing of data on a PSTN-based network H04M11/00; home network gateways H04L12/2834; wireless access networks H04W
• CPC Class Codes: H04L 12/289 Single service
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 2012/6478 Digital subscriber line, e.g. DSL, ADSL, HDSL, XDSL, VDSL
• CPC Class Codes: H04L 27/2601 Multicarrier modulation systems
• CPC Class Codes: H04L 27/2626 Arrangements specific to the transmitter only
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04M 11/062 using different frequency bands for speech and other data
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A logical pipeline or logical hybrid pipeline is used for an xDSL communication system, and particularly for processing DMT symbols. This flexible arrangement permits easy and efficient sequencing of DMT symbols for transmit/receive tasks, and for multiple ports, since the pipeline resources can be shared or allocated as needed to support a particular data transmission. Each stage in the pipelines works on input data objects, and creates output data objects in the same format for use by other stages. The data objects are based on DMT symbols, so this facilitates intelligent control and sequencing of a DMT data transmission. The combination of the pipeline and the tailored data objects permits an implementation of a customized xDSL symbol processor.

Claims

1. A discrete multi-tone (DMT) symbol processor for use in a multi-port xDSL communications system, the processor comprising:

a first buffer stage for receiving a plurality of DMT symbols to be processed in accordance with a predetermined set of operations so as to extract a plurality of data streams for a plurality of corresponding communications ports; and

a first set of hardware based execution units, each of said hardware based execution units being configured to perform a first group of physical layer and/or a transport convergence layer related operations as part of said predetermined set of operations; and

a second set of software based execution units, each of said software based execution units also being configured to perform a second group of physical layer and/or a transport convergence layer operation as part of said predetermined set of operations; and

said first set of hardware based execution units and said second set of software based execution units being interconnected so as to perform all of said predetermined set of operations for all of said plurality of corresponding communications ports;

wherein a plurality of symbols for a plurality of different communications ports are processed simultaneously within the DMT symbol processor.

2. The DMT symbol processor of claim 1, wherein said DMT symbols include both receive and transmit symbols.

3. The DMT symbol processor of claim 1 including a common clock used to initiate said predetermined set of operations by both said first set of hardware based execution units and said second set of software based execution units.

4. The DMT symbol processor of claim 1 including a common memory used by said first set of hardware based execution units and said second set of software based execution units for exchanging data.

5. The DMT symbol processor of claim 4, wherein two separate pages are set up in said common memory for exchanging data, such that at any given time both first set of hardware based execution units and said second set of software based execution units receive input from a first page, and generate output to a second page.

6. The DMT symbol processor of claim 4, wherein said first set of hardware based execution units and said second set of software based execution units are synchronized to the same memory pages such that one or more of said hardware based execution units can be added or dropped as needed to support modifications to said predetermined set of operations.

7. The DMT symbol processor of claim 1 wherein said first set of hardware based execution units are comprised of a plurality of application specific (ASIC) hardware blocks.

8. The DMT symbol processor of claim 7 wherein said second set of software based execution units are comprised of a plurality of DSP cores executing a general purpose DSP instruction set.

9. The DMT symbol processor of claim 8 wherein said first set of hardware based execution units further include a field programmable gate array.

10. The DMT symbol processor of claim 7, wherein said ASIC hardware blocks are interconnected through a first bus that is separate from a second bus used by said plurality of DSP cores.

11. The DMT symbol processor of claim 1, wherein said first set of hardware based execution units and/or said second set of software based execution units can by dynamically adjusted to accommodate a change in said predetermined set of operations, and/or a data rate requirement for said plurality of different communications ports.

12. The DMT symbol processor of claim 1, wherein a clock rate used by said first set of hardware based execution units and said second set of software based execution units is higher than that required by an xDSL communications protocol supported by said plurality of corresponding communication ports.

13. A processing pipeline for processing a discrete multi-tone (DMT) based data transmission comprising:

a first buffer for receiving DMT symbols associated with a communications transmission transporting a data stream, said communications transmission requiring a set of predefined signal processing operations to extract said data stream from said DMT symbols; and

a plurality of interconnected pipeline stages, each of said pipeline stages being adapted for performing at least one processing operation associated with said set of predefined signal processing operations for the DMT symbol;

a second buffer for receiving an output from said plurality of interconnected pipeline stages, said output corresponding to data in said data stream;

wherein at least one of said pipeline stages is implemented in hardware, and at least one other of said pipeline stages is implemented in software, and with results exchanged directly between such hardware and software pipeline stages such that a logical hybrid pipeline is effectuated for performing said set of predefined signal processing operations to extract said data stream.

14. The processing pipeline of claim 13, wherein time dependencies between successively received DMT symbols are eliminated for said communications transmission.

15. The processing pipeline of claim 13, wherein computing resources for a physical medium dependent layer, a transport convergence layer and a microprocessor subsystem are allocated as required to support a computation requirement for said data transmission.

16. The processing pipeline of claim 13 wherein said data stream is a bit stream, a packet based stream, or a cell based stream.

17. The processing pipeline of claim 13 wherein said data stream is based on transporting asynchronous transfer mode (ATM) cells over a digital subscriber loop (DSL).

18. The processing pipeline of claim 13 further including a common pipeline memory shared by said plurality of interconnected pipeline stages for storing intermediate results associated with said set of predefined signal processing operations.

19. The processing pipeline of claim 13 wherein said plurality of interconnected pipeline stages operate on a number of different DMT based symbols within a single pipeline clock period.

20. The processing pipeline of claim 13 wherein a plurality of data streams for a plurality of communications port are processed simultaneously.

21. The processing pipeline of claim 13, wherein M separate pipeline stages are used to support n separate ports, such that when a number of distinct operations associated with said set of predefined signal processing operations for the DMT symbol is equal to N, then M<

N*n.

22. A discrete multi-tone (DMT) instruction processor for processing a DMT based data transmission comprising:

a first buffer for receiving DMT symbols associated with a communications transmission transporting a data stream, wherein a set of predefined signal processing operations are required extract said data stream from said DMT symbols; and

a plurality of interconnected pipeline stages, each of said pipeline stages being adapted for executing a DMT related instruction, said DMT related instruction specifying a DMT related operation and at least one associated DMT related operand for processing a DMT symbol;

a second buffer for receiving an output from said plurality of interconnected pipeline stages, said output corresponding to data in said data stream;

wherein at least one of said pipeline stages is implemented in hardware, and at least one other of said pipeline stages is implemented in software;

and further wherein said plurality of interconnected pipeline stages performs substantially all of said set of predefined signal processing operations to extract said data stream.

23. The DMT instruction processor of claim 22 wherein each of said pipeline stages generates an output also in the form of a DMT related instruction for use by a subsequent pipeline stage.

24. The DMT instruction processor of claim 22 wherein a plurality of separate DMT symbols are processed within a single pipeline clock period, such that the DMT instruction processor behaves like a superscalar DMT instruction processor.

25. The DMT instruction processor of claim 22 wherein each of said pipeline stages receives, decodes and executes a separate DMT instruction within a single pipeline clock period, such that a plurality of DMT symbols are processed at the same time within the DMT instruction processor.

26. The DMT instruction processor of claim 22 wherein at least one of said plurality of pipeline stages is adapted to execute at least two different types of Doff related instructions.

27. The DMT instruction processor of claim 22 wherein time dependencies between successive DMT symbols are eliminated.

28. The DMT instruction processor of claim 22 wherein said plurality of pipeline stages simultaneously handle both receive DMT related instructions and transmit DMT related instructions for receive and transmit operations respectively.

29. The DMT instruction processor of claim 22 wherein said plurality of pipeline stages simultaneously handle DMT related instructions for both an ATU-C and an ATU-R transceiver.

30. The DMT instruction processor of claim 22 wherein said plurality of pipeline stages can by dynamically adjusted for a data transmission to provide a scalable DMT processing architecture by changing a number of said plurality of pipeline stages, and/or computing resources available to said plurality of pipeline stages, and/or a clock rate used by said plurality of pipeline stages.

31. The DMT instruction processor of claim 22 wherein said plurality of pipeline stages implement DMT related instructions for a physical medium dependent layer and a transport convergence layer.

32. The DMT instruction processor of claim 31, wherein said transport convergence layer includes asynchronous transfer mode (ATM) specific operations.

33. A method of operating a discrete multi-tone (DMT) communications system having a plurality of communications ports, the method comprising the steps of:

dividing a receive task and a transmit task for each port of the plurality of communications ports into a set of receive operations and transmit operations respectively; and

using a shared processing pipeline to perform both said receive operations and transmit operations; and

providing a first type of computing resource for said shared processing pipeline, such that each pipeline stage of said first type of computing resource can perform at least one of said receive operations or at least one of said transmit operations; and

providing a second type of computing resource for said shared processing pipeline, such that each pipeline stage of said second type of computing resource can perform at least one of said receive operations and at least one of said transmit operations;

wherein said shared processing pipeline is used for said receive task and said transmit task for each port of the plurality of communications ports.

34. The method of claim 33, wherein said receive task and said transmit task are associated with an xDSL based transmission.

35. The method of claim 33, wherein said first type of computing resource and said second type of computing resource can be allocated as needed by the discrete multi-tone (DMT) communications system to support a communications mode implemented by each port of the plurality of communications ports.

36. The method of claim 33, wherein said receive task and said transmit task can be allocated differing amounts of said first type of computing resource and said second type of computing resource.

37. The method of claim 33, wherein said shared processing pipeline includes a combination of hardware and software processing circuits.

38. A method of operating a discrete multi-tone (DMT) symbol processor for use in a multi-port xDSL communications system, the method comprising the steps of:

buffering a plurality of DMT symbols to be processed in accordance with a predetermined set of operations so as to extract a plurality of data streams for a plurality of corresponding communications ports; and

configuring a first set of hardware based execution units to perform a first group of physical layer and/or a transport convergence layer related operations as part of said predetermined set of operations; and

configuring a second set of software based execution units to perform a second group of physical layer and/or a transport convergence layer operations as part of said predetermined set of operations; and

exchanging computation results of said predetermined set of operations between said first set of hardware based execution units and said second set of software based execution units;

simultaneously processing a plurality of symbols for a plurality of different communications ports within the DMT symbol processor, so that all of said predetermined set of operations for all of said plurality of corresponding communications ports are performed by said first set of hardware based execution units and said second set of software based execution units.

39. The method of claim 38, wherein said DMT symbols include both receive and transmit symbols.

40. The method of claim 38 further including a step:

initiating said predetermined set of operations by both said first set of hardware based execution units and said second set of software based execution units using a common clock.

41. The method of claim 38 wherein said computation results are exchanged through a common memory.

42. The method of claim 38, further including a step:

providing a first local control bus for said first set of hardware execution units that is separate from a second local control bus used by said second set of software based execution units.

43. The method of claim 38, wherein said first set of hardware based execution units and/or said second set of software based execution units can by dynamically adjusted to accommodate a change in said predetermined set of operations, and/or a data rate requirement for said plurality of different communications ports.

44. The method of claim 40, wherein said common clock uses a clock rate higher than that required by an xDSL communications protocol supported by said plurality of corresponding communication ports.

45. A method of operating a processing pipeline used for processing a discrete multi-tone (DMT) based data transmission the method comprising the steps of:

buffering received DMT symbols associated with a communications transmission transporting a data stream, said communications transmission requiring a set of predefined signal processing operations to extract said data stream from said DMT symbols; and

coupling a plurality of pipeline stages to perform said set of predefined signal processing operations, such that each of said pipeline stages is adapted for performing at least one processing operation associated with said set of predefined signal processing operations for the DMT symbol;

buffering an output from said plurality of interconnected pipeline stages, said output corresponding to data in said data stream;

wherein at least one of said pipeline stages is implemented in hardware, and at least one other of said pipeline stages is implemented in software, such that a logical pipeline is effectuated for performing said set of predefined signal processing operations to extract said data stream.

46. The method of claim 45, wherein time dependencies between successively received DMT symbols are eliminated for said communications transmission.

47. The method of claim 45, wherein computing resources for a physical medium dependent layer, a transport convergence layer and a microprocessor subsystem forming said plurality of pipeline stages are allocated as required to support a computation requirement for said communications transmission.

48. The method of claim 45 wherein said data stream is a bit stream, a packet based stream, or a cell based stream.

49. The method of claim 45 wherein said data stream is based on transporting asynchronous transfer mode (ATM) cells over a digital subscriber loop (DSL).

50. The method of claim 45 wherein said plurality of pipeline stages operate on a number of different DMT based symbols within a single pipeline clock period.

51. The method of claim 45 wherein a plurality of data streams for a plurality of communications ports are processed simultaneously.

52. The method of claim 45, further including a step:

providing M separate pipeline stages to support n separate communications ports, such for a number of distinct operations N associated with said set of predefined signal processing operations for the DMT symbol M<

N*n.

53. A method of implementing a discrete multi-tone (DMT) instruction processor for processing a DMT based data transmission comprising the steps of:

receiving DMT symbols associated with a communications transmission transporting a data stream, wherein a set of predefined signal processing operations are required to extract said data stream from said DMT symbols; and

coupling a plurality of pipeline stages to perform said set of predefined signal processing operations, said pipeline stages being implemented in a combination fo hardware and software; and

executing a DMT related instruction within said plurality of pipeline stages, said DMT related instruction specifying a DMT related operation and at least one associated DMT related operand for processing a DMT symbol; and

receiving an output from said plurality of interconnected pipeline stages, said output corresponding to data in said data stream;

wherein said plurality of pipeline stages performs substantially all of said set of predefined signal processing operations to extract said data stream.

54. The method of claim 53 wherein each of said pipeline stages generates an output also in the form of a DMT related instruction for use by a subsequent pipeline stage.

55. The method of claim 53 wherein a plurality of separate DMT symbols are processed within a single pipeline clock period, such that the DMT instruction processor behaves like a superscalar DMT instruction processor.

56. The method of claim 53 wherein each of said pipeline stages receives, decodes and executes a separate DMT instruction within a single pipeline clock period, such that a plurality of DMT symbols are processed at the same time within the DMT instruction processor.

57. The method of claim 53 wherein at least one of said plurality of pipeline stages is adapted to execute at least two different types of DMT related instructions.

58. The method of claim 53 wherein time dependencies between successive DMT symbols are eliminated.

59. The method of claim 53 wherein said plurality of pipeline stages simultaneously handle both receive DMT related instructions and transmit DMT related instructions for receive and transmit operations respectively.

60. The method of claim 53 wherein said plurality of pipeline stages simultaneously handle DMT related instructions for both an ATU-C and an ATU-R transceiver.

61. The method of claim 53 wherein said plurality of pipeline stages can by dynamically adjusted for a data transmission to provide a scalable DMT processing architecture by changing a number of said plurality of pipeline stages, and/or computing resources available to said plurality of pipeline stages, and/or a clock rate used by said plurality of pipeline stages.

62. The method of claim 53 wherein said plurality of pipeline stages implement DMT related instructions for a physical medium dependent layer and a transport convergence layer.

63. The method of claim 62, wherein said transport convergence layer includes asynchronous transfer mode (ATM) specific operations.