Method of designing a layout of an LSI chip, and a computer product

• US 20020004929A1
• Filed: 02/22/2001
• Published: 01/10/2002
• Est. Priority Date: 07/04/2000
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Abe, Koji, Osaki, Seiko
• Granted Patent: US 6,564,362 B2
• Time in Patent Office: Days
• US Class Current: 716/10
• CPC Class Codes: G01R 31/318538 Topological or mechanical aspects
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures

Abstract

In a method of designing a layout of an LSI chip, which LSI chip has boundary scan registers, after arranging I/O cells and before arranging an internal logic circuit and the like, I/O connection boundary scan registers are preferentially arranged in empty regions of the I/O cells. Output I/O control boundary scan registers are arranged at intermediate points between the I/O connection boundary scan registers, respectively, or a chip side closer to the intermediate points. Thereafter, before arranging cells constituting other circuits and creating a wiring pattern, buffer cells are inserted into nets of test signals to the boundary scan register led to a test control circuit.

Claims

1. A method of designing a layout of an LSI chip, said LSI chip having boundary scan registers, the method comprising the steps of:

arranging I/O cells;

arranging I/O connection boundary scan registers to be connected to the I/O cells, in empty regions near the connection target I/O cells among a group of said arranged I/O cells;

arranging an output I/O control boundary scan registers to be connected to the I/O connection boundary scan registers, based on arrangement positions of a plurality of connection target I/O connection boundary scan registers among a group of said arranged I/O connection boundary scan registers;

making a fan-out adjustment to said arranged I/O connection boundary scan registers and output I/O control boundary scan registers;

arranging cells constituting other circuits in empty regions; and

creating a wiring pattern.

2. The method of designing a layout of an LSI chip according to claim 1, wherein

said output I/O control boundary scan registers are arranged at intermediate points between a plurality of connection target I/O connection boundary scan registers, respectively.

3. The method of de-signing a layout of an LSI chip according to claim 1, wherein

if a plurality of I/O connection boundary scan registers to which the output I/O control boundary scan registers are connected, are arranged along a pair of adjacent chip sides, said output I/O control boundary scan registers are arranged toward the chip side closer to the intermediate points between said plurality of connection target I/O connection boundary scan registers out of said pair of chip sides.

4. The method of designing a layout of an LSI chip according to claim 1, wherein

the fan-out adjustment is made by calculating a tentative wiring length between the boundary scan registers arranged adjacent each other based on Manhattan lengths of said boundary scan registers, calculating an estimated wiring capacity based on the tentative wiring length, and inserting buffer cells into test signal nets based on the estimated wiring capacity so that loads of input terminals of the boundary scan registers driven by the buffer cell fall within a range of driving capabilities of output terminals of said buffer cells.

5. The method of designing a layout of an LSI chip according to claim 4, wherein

a correction coefficient for correcting a difference between the tentative wiring length and an actual wiring length is obtained in advance, and the driving capabilities of the output terminals of said buffer cells are corrected using the correction coefficient.

6. The method of designing a layout of an LSI chip according to claim 4, wherein

said buffer cell is arranged near the boundary scan register closest to a test control circuit among one or a plurality of boundary scan registers driven by said buffer cells.

7. A computer readable medium for storing instructions, which when executed on a computer, causes the computer to perform the steps of:

arranging I/O cells;

arranging I/O connection boundary scan registers to be connected to the I/O cells, in empty regions near the connection target I/O cells among a group of said arranged I/O cells;

arranging output I/O control boundary scan registers to be connected to the I/O connection boundary scan registers, based on arrangement positions of a plurality of corresponding connection target I/O connection boundary scan registers among a group of said arranged I/O connection boundary scan registers;

making a fan-out adjustment to said arranged I/O connection boundary scan registers and output I/O control boundary scan registers;

arranging cells constituting other circuits in empty regions; and

creating a wiring pattern.

8. A computer readable recording medium according to claim 7, wherein

the computer program allows the computer to make the fan-out adjustment by calculating a tentative wiring length between the boundary scan registers arranged adjacent each other based on Manhattan lengths of said boundary scan registers, calculating an estimated wiring capacity based on the tentative wiring length, and inserting buffer cells into test signal nets based on the estimated wiring capacity so that loads of input terminals of the boundary scan registers driven by the buffer cells fall within a range of driving capabilities of output terminals of said buffer cell.