FPGA with a plurality of input reference voltage levels

• US 20020005735A1
• Filed: 08/07/2001
• Published: 01/17/2002
• Est. Priority Date: 04/11/1997
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Frake, Scott O., Young, Steven P., Goetting, F. Erich, Kondapalli, Venu M.
• Granted Patent: US 6,448,809 B2
• Time in Patent Office: Days
• US Class Current: 326/39
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17788 for input/output [I/O] voltages

Abstract

The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

Claims

1. An input/output (I/O) block structure for a programmable logic device, the structure including:

a plurality of I/O blocks divided into groups of I/O blocks, each group having a separate output supply voltage;

a plurality of output supply voltage pads divided into sets, wherein pads providing different output supply voltages are in separate sets; and

configurable means for connecting each group of I/O blocks to at least one pad in a set.

2. The I/O block structure of claim 1, wherein each I/O block includes:

an input buffer driven by a pad line;

an output buffer driving the pad line, the output buffer comprising a plurality of configurable pullups and a plurality of configurable pulldowns.

3. The I/O block structure of claim 2, wherein the configurable pullups and configurable pulldowns include configuration logic controlled by one or more configuration memory cells.

4. The I/O block structure of claim 2, wherein the input buffer includes:

a plurality of input paths; and

a plurality of configuration memory cells for configuring the input buffer to select one of the plurality of input paths.

5. The I/O block structure of claim 4, wherein the input buffer further includes:

level selecting means on at least one input path, the level selecting means receiving a reference voltage for setting a trip point between high and low voltage levels on the pad line, thereby providing an appropriate output signal from the input buffer.

6. The I/O block structure of claim 5, wherein the level selecting further includes means for configurably disabling the level selecting means.

7. The I/O block structure of claim 6, wherein the level selecting means includes a differential amplifier, and wherein the means for configurably disabling includes a configuration memory cell controlling a transmission gate in the differential amplifier.

8. The I/O block structure of claim 2, wherein the input buffer includes a differential amplifier having a reference input, and wherein the I/O block further includes means for configurably applying a voltage level on one of a plurality of reference voltage lines to the reference input.

9. The I/O block structure of claim 8, wherein the means for configurably applying includes a multiplexer controlled by one or more configuration memory cells.

10. The I/O block structure of claim 8, further including means for configurably connecting the pad line to at least one of the plurality of reference voltage lines, the means for configurably connecting including a transmission gate controlled by a configuration memory cell.

11. An input/output (I/O) block structure for a programmable logic device, the structure including:

a plurality of I/O blocks divided into groups of I/O blocks, each group having a separate input reference voltage;

a plurality of input reference voltage pads divided into sets, wherein pads providing different input reference voltages are in separate sets; and

configurable means for connecting each group of I/O blocks to at least one pad in a set.