Semiconductor device and the manufacturing method thereof

• US 20020006693A1
• Filed: 07/12/2001
• Published: 01/17/2002
• Est. Priority Date: 07/13/2000
• Status: Abandoned Application

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Matsuda, Tomoko
• Application Number:
  US09/902,704
• Publication Number:
  US 20020006693A1
• Time in Patent Office: Days
• US Class Current: 438/180
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence

Abstract

A manufacturing method that prevents an enhanced diffusion while preventing channeling from occurring, and forms a local channel having a steep impurity concentration distribution with precise positioning. After forming a sacrifice film on the surface of a silicon substrate, ion implantation is performed from a perpendicular direction through a resist film mask to form a local channel. The thickness of the sacrifice film is greater than or equal to 10 nm and less than or equal to 100 nm. Indium is used as an ion species of the ion implantation.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a sacrifice film having a thickness greater than or equal to 10 nm and less than or equal to 100 nm on a semiconductor substrate;

providing a resist film having an opening on said sacrifice film; and

providing an impurity doped region by performing an ion implantation through said sacrifice film from a direction substantially perpendicular to said semiconductor substrate with using said opening in said resist film as a mask.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein said sacrifice film is a silicon oxide film.

3. The method of manufacturing a semiconductor device as claimed in claim 2, wherein said sacrifice film is formed by thermal oxidation.

4. The method of manufacturing a semiconductor device as claimed in claim 1, wherein said impurity doped region is formed under a condition of d≧

0.035V+4.75, where d (nm) is said thickness of said sacrifice film and V (keV) is an implant energy of said ion implantation.

5. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising implanting an impurity into said sacrifice film so as to make a defect in said sacrifice film.

6. The method of manufacturing a semiconductor device as claimed in claim 5, wherein said implanting an impurity into said sacrifice film is performed so as to prevent said semiconductor substrate from having a defect.

7. The method of manufacturing a semiconductor device as claimed in claim 5, wherein said impurity implanted into said sacrifice film is silicon.

8. The method of manufacturing a semiconductor device as claimed in claim 5, wherein said impurity implanted into said sacrifice film is germanium.

9. The method of manufacturing a semiconductor device as claimed in claim 8, wherein a dosed amount of said germanium is between 1×

10^—

cm<sup>−

2</sup> and 5×

10¹⁴ cm<sup>−

2</sup>.

10. The method of manufacturing a semiconductor device as claimed in claim 1, wherein said impurity doped region comprises indium.

11. The method of manufacturing a semiconductor device as claimed in claim 1, wherein said impurity doped region is a local cannel region, the method further comprising:

providing a gate electrode on said semiconductor substrate; and

providing a source region and a drain region, at both sides of said gate electrode so that said source region and said drain region contact with said local channel.

12. The method of manufacturing a semiconductor device as claimed in claim 11, wherein:

said source region comprises a highly doped region and an extension region, and

said local channel contacts with said highly doped region and said extension region.

13. The method of manufacturing a semiconductor device as claimed in claim 11, wherein:

said source region comprises a highly doped region and an extension region, and

said local channel contacts with said extension region.

14. The method of manufacturing a semiconductor device as claimed in claim 1, wherein said direction is less than 2 degrees from perpendicular relative to said semiconductor substrate.

15. The method of manufacturing a semiconductor device as claimed in claim 1, wherein said impurity doped region is one of a group consisting indium, arsenic or phosphorus.

16. A method of manufacturing a semiconductor device, comprising:

providing a sacrifice film on a semiconductor substrate;

providing a resist film having an opening on said sacrifice film; and

providing an impurity doped region by performing an ion implantation through said sacrifice film from a direction substantially perpendicular to the semiconductor substrate with using said opening in said resist film as a mask, under a condition of d≧

0.035V+4.75, where d (nm) is a thickness of said sacrifice film and V (keV) is an implant energy upon said ion implantation.

17. The method of manufacturing a semiconductor device as claimed in claim 16, wherein said sacrifice film is a silicon oxide film.

18. The method of manufacturing a semiconductor device as claimed in claim 16, wherein said sacrifice film is formed by thermal oxidation.

19. The method of manufacturing a semiconductor device as claimed in claim 16, further comprising implanting an impurity into said sacrifice film.

20. The method of manufacturing a semiconductor device as claimed in claim 19, wherein said impurity doped into said sacrifice film is germanium.

21. The method of manufacturing a semiconductor device as claimed in claim 19, wherein said impurity doped into said sacrifice film is silicon.

22. The method of manufacturing a semiconductor device as claimed in claim 20, wherein a dosed amount of said germanium is between 1×

10¹³ cm<sup>−

2</sup> and 5×

10¹⁴ cm<sup>−

2</sup>.

23. The method of manufacturing a semiconductor device as claimed in claim 16, wherein said impurity doped region comprises indium.

24. The method of manufacturing a semiconductor device as claimed in claim 16, wherein said impurity doped region is one of a group consisting indium, arsenic or phosphorus.