×

Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor

  • US 20020006699A1
  • Filed: 04/17/2000
  • Published: 01/17/2002
  • Est. Priority Date: 10/06/1997
  • Status: Active Grant
First Claim
Patent Images

1. A memory cell for a memory array in a folded bit line configuration, the memory cell comprising:

  • an access transistor formed in a pillar of single crystal semiconductor material, the access transistor having first and second source/drain regions and a body region that are vertically aligned;

    the access transistor further including a gate coupled to a word line disposed adjacent to the body region;

    a passing word line separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell; and

    a trench capacitor, wherein the trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×