Load capacitance measuring circuit and output buffer adaptive to wide range of load capacitance
First Claim
1. A load capacitance measuring circuit comprising:
- a reference capacitor;
a constant current source connected in series with said reference capacitor, for generating a reference voltage with a constant gradient in said reference capacitor;
a load resistor; and
a transistor having its source connected to a capacitive load to be measured, its gate connected to a connecting point of said reference capacitor and said constant current source to be supplied with the reference voltage, and its drain connected to a voltage source via said load resistor, wherein a capacitance of the capacitive load is obtained from the drain voltage of said transistor and the gradient of the reference voltage.
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Accused Products
Abstract
An output buffer includes a reference capacitor; a constant current source connected in series with the reference capacitor, for generating a reference voltage with a constant gradient by charging the reference capacitor; a first transistor having its source connected to a capacitive load, and its gate connected to the connecting point of the reference capacitor and the first constant current source to be supplied with the reference voltage; a second transistor connected between the drain of the first transistor and a voltage source; a third transistor connected between the capacitive load and the voltage source; and a fourth transistor connected to the control terminal of the second transistor and to the control terminal of the third transistor, for switching the second and third transistors from an OFF state to an ON state when the first transistor is turned on. It solves a problem of a conventional output buffer in that when the load capacitance of an external circuit differs from a presupposed one, it cannot meet the specification of the slew rate, or can consume excessive power.
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Citations
13 Claims
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1. A load capacitance measuring circuit comprising:
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a reference capacitor;
a constant current source connected in series with said reference capacitor, for generating a reference voltage with a constant gradient in said reference capacitor;
a load resistor; and
a transistor having its source connected to a capacitive load to be measured, its gate connected to a connecting point of said reference capacitor and said constant current source to be supplied with the reference voltage, and its drain connected to a voltage source via said load resistor, wherein a capacitance of the capacitive load is obtained from the drain voltage of said transistor and the gradient of the reference voltage. - View Dependent Claims (2, 3)
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4. An output buffer comprising:
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a reference capacitor;
a first constant current source connected in series with said reference capacitor, for generating a reference voltage with a constant gradient by charging said reference capacitor;
a first transistor having its source connected to a capacitive load, and its gate connected to a connecting point of said reference capacitor and said first constant current source to be supplied with the reference voltage;
a first switching device connected between the drain of said first transistor and a voltage source;
a second switching device connected between the capacitive load and the voltage source; and
a first driver connected to a control terminal of said first switching device and to a control terminal of said second switching device, for switching said first switching device and said second switching device from an OFF state to an ON state when said first transistor is turned on. - View Dependent Claims (5, 6, 7, 8)
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9. An output buffer comprising:
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a reference capacitor;
a first constant current source connected in series with said reference capacitor, for generating a reference voltage with a constant gradient by charging said reference capacitor;
a first transistor having its source connected to a capacitive load, and its gate connected to a connecting point of said reference capacitor and said first constant current source to be supplied with the reference voltage;
a first switching device connected between the drain of said first transistor and a voltage source;
a second switching device connected between the capacitive load and the voltage source; and
a third switching device that is connected between a control terminal of said first switching device and a control terminal of said second switching device, and controlled by a voltage across the capacitive load. - View Dependent Claims (10, 11, 12, 13)
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Specification