High speed precision pseudo random noise shift control for fast multiple channel global positioning system signal re-tracking

• US 20020009126A1
• Filed: 03/13/2001
• Published: 01/24/2002
• Est. Priority Date: 03/13/2000
• Status: Active Grant

• Current Assignee: PRI Research & Development Corp.
• Original Assignee: PRI Research & Development Corp.
• Inventors: Mehrnia, Alireza, Shakeri, Kaveh
• Granted Patent: US 7,184,461 B2
• Time in Patent Office: Days
• US Class Current: 375/140
• CPC Class Codes: G01S 19/24 Acquisition or tracking or demodulation of signals transmitted by the system synchronisation aspects of direct sequence spread spectrum modulation H04B1/7073
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: H04B 1/707 using direct sequence modulation

Abstract

One embodiment of the present invention includes a control circuit, an increment register, and an accumulator. The control circuit generates a channel enable signal based on control information from a processor at a first clock signal having a first clock frequency. The channel enable signal selects a channel for a satellite in a global positioning system (GPS). The channel operates at a coarse/acquisition (C/A) clock signal having a second clock frequency. The increment register stores an increment value for the selected channel at the first clock signal. The accumulator generates a pseudo-random noise (PN) clock signal to a PN generator using the increment value.

Claims

1. An apparatus comprising:

a control circuit to generate a channel enable signal based on control information from a processor at a first clock signal having a first clock frequency, the channel enable signal selecting a channel for a satellite in a global positioning system (GPS), the channel operating at a coarse/acquisition (C/A) clock signal having a second clock frequency;

an increment register to store an increment value for the selected channel at the first clock signal; and

an accumulator coupled to the increment register and the control circuit to generate the PN clock signal using the increment value.

2. The apparatus of claim 1 wherein the control information includes at least one of channel select information, an initial count, the increment value, and PN command.

3. The apparatus of claim 2 wherein the control circuit comprises:

a decoder to decode the channel select information, the decoded channel select information providing the channel enable signal;

a channel enable register coupled to the decoder to store the channel enable signal at the first clock signal;

a counter coupled to the channel enable register to update a count from the initial count at the first clock signal, the counter generating a terminal signal when the count reaches a terminal count; and

a logic circuit coupled to the counter and the channel enable register to generate a load signal from the PN command to load the initial count to the counter and a reset signal from the terminal signal to reset the channel enable register.

4. The apparatus of claim 2 wherein the accumulator comprises:

an accumulating register to store a numerically controlled oscillator (NCO) value at a current cycle of the first clock signal, the NCO value providing the PN clock; and

an adder coupled to the accumulating register and the increment register to generate a sum of the increment value and the NCO value using a shift command from the PN command, the sum being loaded into the accumulating register and corresponding to the NCO value at a next cycle of the first clock signal.

5. The apparatus of claim 4 wherein the adder shifts the increment value in a direction according to the shift command.

6. The apparatus of claim 5 wherein the adder shifts the increment value one bit to the left if the shift command is a left shift command.

7. The apparatus of claim 5 wherein the adder shifts the increment value one bit to the right if the shift command is a right shift command.

8. The apparatus of claim 4 wherein a most significant bit (MSB) of the NCO value provides the PN clock to the PN generator.

9. The apparatus of claim 1 wherein the first and second clock frequencies are approximately 8.184 MHz and 1.023 MHz, respectively.

10. The apparatus of claim 1 wherein the channel enable signal is one of twelve enable signals corresponding to twelve satellites in the GPS.

11. A method comprising:

generating a channel enable signal based on control information from a processor at a first clock signal having a first clock frequency, the channel enable signal selecting a channel for a satellite in a global positioning system (GPS), the channel operating at a coarse/acquisition (C/A) clock signal having a second clock. frequency;

storing an increment value for the selected channel at the first clock signal; and

generating a pseudo-random noise (PN) clock signal to a PN generator using the increment value.

12. The method of claim 11 wherein the control information includes at least one of channel select information, an initial count, the increment value, and PN command.

13. The method of claim 12 wherein generating the channel enable signal comprises:

decoding the channel select information, the decoded channel select information providing the channel enable signal;

storing the channel enable signal at the first clock signal;

updating a count from the initial count at the first clock signal to generate a terminal signal when the count reaches a terminal count; and

generating a load signal from the PN command to load the initial count to the counter and a reset signal from the terminal signal to reset the channel enable register.

14. The method of claim 12 wherein generating the PN clock comprises:

storing a numerically controlled oscillator (NCO) value at a current cycle of the first clock signal in an accumulating register, the NCO value providing the PN clock; and

generating a sum of the increment value and the NCO value using a shift command from the PN command, the sum being loaded into the accumulating register and corresponding to the NCO value at a next cycle of the first clock signal.

15. The method of claim 14 wherein generating the sum comprises shifting the increment value in a direction according to the shift command.

16. The method of claim 15 wherein shifting the increment value comprises shifting the increment value one bit to the left if the shift command is a left shift command.

17. The method of claim 15 wherein shifting the increment value comprises shifting the increment value one bit to the right if the shift command is a right shift command.

18. The method of claim 14 wherein a most significant bit (MSB) of the NCO value provides the PN clock to the PN generator.

19. The method of claim 11 wherein the first and second clock frequencies are approximately 8.184 MHz and 1.023 MHz, respectively.

20. The method of claim 11 wherein the channel enable signal is one of twelve enable signals corresponding to twelve satellites in the GPS.

21. A receiver comprising:

a processor to generate control information;

a pseudo-random noise (PN) code generator to generate a PN sequence at a PN clock signal to a correlator of a global positioning system (GPS) base-band system; and

a code numerically controlled oscillator (NCO) coupled to the PN code generator and the processor to generate the PN clock signal based on the control information, the code NCO comprising;

a control circuit to generate a channel enable signal based on the control information at a first clock signal having a first clock frequency, the channel enable signal selecting a channel for a satellite in a global positioning system (GPS), the channel operating at a coarse/acquisition (C/A) clock signal having a second clock frequency,

an increment register to store an increment value for the selected channel at the first clock signal, and

an accumulator coupled to the increment register and the control circuit to generate the PN clock signal using the increment value.

22. The receiver of claim 21 wherein the control information includes at least one of channel select information, an initial count, the increment value, and PN command.

23. The receiver of claim 22 wherein the control circuit comprises:

a decoder to decode the channel select information, the decoded channel select information providing the channel enable signal;

a channel enable register coupled to the decoder to store the channel enable signal at the first clock signal;

a counter coupled to the channel enable register to update a count from the initial count at the first clock signal, the counter generating a terminal signal when the count reaches a terminal count; and

a logic circuit coupled to the counter and the channel enable register to generate a load signal from the PN command to load the initial count to the counter and a reset signal from the terminal signal to reset the channel enable register.

24. The receiver of claim 22 wherein the accumulator comprises:

an accumulating register to store a numerically controlled oscillator (NCO) value at a current cycle of the first clock signal, the NCO value providing the PN clock; and

an adder coupled to the accumulating register and the increment register to generate a sum of the increment value and the NCO value using a shift command from the PN command, the sum being loaded into the accumulating register and corresponding to the NCO value at a next cycle of the first clock signal.

25. The receiver of claim 24 wherein the adder shifts the increment value in a direction according to the shift command.

26. The receiver of claim 25 wherein the adder shifts the increment value one bit to the left if the shift command is a left shift command.

27. The receiver of claim 25 wherein the adder shifts the increment value one bit to the right if the shift command is a right shift command.

28. The receiver of claim 24 wherein a most significant bit (MSB) of the NCO value provides the PN clock to the PN generator.

29. The receiver of claim 21 wherein the first and second clock frequencies are approximately 8.184 MHz and 1.023 MHz, respectively.

30. The receiver of claim 21 wherein the channel enable signal is one of twelve enable signals corresponding to twelve satellites in the GPS.