Method and apparatus for operating a PLL for synthesizing high-frequency signals for wireless communications

• US 20020009984A1
• Filed: 08/20/2001
• Published: 01/24/2002
• Est. Priority Date: 05/29/1998
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Wang, Caiyi, Welland, David R.
• Granted Patent: US 6,549,765 B2
• Time in Patent Office: Days
• US Class Current: 455/260
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may be controlled by a plurality of analog control signals. The analog control signals may be derived by first generating a plurality of phase shifted signals from a divided version of the VCO output clock. Second, the phase differences between the plurality of phase shifted signals and a divided version of a reference clock may be detected and then converted to the analog control signals.

Claims

1. A wireless communication frequency synthesizer having a phase locked loop, comprising:

a controllable oscillator;

a first clock node coupled to an output of the controllable oscillator;

a second clock node coupled to a reference clock;

a plurality of phase shifted signals, the phase shifted signals being generated from, at least in part, a first clock signal on the first clock node; and

a plurality of variable control signals, the variable control signals being generated from a detected phase difference between at least some of the plurality of phase shifted signals and a second clock signal on the second clock node, the control signals coupled to inputs of the controllable oscillator.

2. A method of operating a wireless communication frequency synthesizer having a phase locked loop, comprising:

generating a plurality of phase shifted signals utilizing a first clock signal, the first clock signal being generated from an output clock signal of phase locked loop;

detecting a phase difference between at least some of the plurality of phase shifted signals and a second clock signal, the second clock signal being generated from a reference clock signal of phase locked loop;

generating a plurality of control signals from the detected phase differences; and

controlling the output frequency of a controllable oscillator of the phase locked loop with the control signals.

3. A wireless communication frequency synthesizer having a phase locked loop, comprising:

a controllable oscillator;

a first clock node coupled to an output of the controllable oscillator;

a second clock node coupled to a reference clock;

a plurality of analog control signals, the analog values of the analog control signals being related to a phase difference between a first clock signal on the first clock node and a second clock signal on the second clock node; and

a plurality of controllable oscillator inputs coupled to the plurality of analog control signals, data on the controllable oscillator inputs controlling the output frequency of the controllable oscillator.

4. A method of operating a wireless communication frequency synthesizer having a phase locked loop, comprising:

detecting a phase difference between at least two signals within the phase locked loop;

generating a plurality of analog control voltages from a result of the phase difference detection;

providing the plurality of analog control voltages to inputs of a controllable oscillator; and

controlling the output frequency of the oscillator with the plurality of analog control voltages.