DMA windowing in an LPAR environment using device arbitration level to allow multiple IOAs per terminal bridge

• US 20020010811A1
• Filed: 01/23/2001
• Published: 01/24/2002
• Est. Priority Date: 06/08/2000
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Thurber, Steven Mark, Arndt, Richard Louis, Neal, Danny Marvin
• Granted Patent: US 6,823,404 B2
• Time in Patent Office: Days
• US Class Current: 710/5
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned data processing system, from fetching or corrupting data from a memory location allocated to another OS image within the data processing system is provided. A hypervisor prevents transmission of data between an input/output adapter in one of the logical partitions and memory locations assigned to other logical partitions during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. The I/O adapters (IOAs) are connected to PCI host bridges via terminal bridges. A single terminal bridge may support multiple IOAs, in which case every terminal bridge has a plurality of sets of range registers, each associated with a respective one of the IOAs to which it is connected. An arbiter is provided which selects one of the input/output adapters to use the PCI bus. The terminal bridge can examine the grant signals from the arbiter to the IOAs, to determine which set of range registers is to be used.

Claims

1. A logically partitioned data processing system, comprising:

a plurality of logical partitions;

a plurality of operating systems, each assigned to one of said plurality of logical partitions;

a plurality of memory locations, each location assigned to one of said plurality of logical partitions;

a data transmission bus;

at least one terminal bridge connected to said data transmission bus;

a plurality of input/output adapters, each associated with a different one of said plurality of logical partitions, said input/output adapters being connected to said terminal bridge; and

means for preventing transmission of data between a given one of said input/output adapters which is associated with a first one of the plurality of logical partitions, and memory locations unassigned to said first one of said plurality of logical partitions.

2. The logically partitioned data processing system of claim 1 wherein said data transmission bus is a PCI bus, and further comprising:

a PCI host bridge connected to said PCI bus; and

an input/output bus connected to said PCI host bridge.

3. The logically partitioned data processing system of claim 1 wherein said terminal bridge has a plurality of sets of range registers, each associated with a respective one of said input/output adapters.

4. The logically partitioned data processing system of claim 3 further comprising an arbiter which selects one of said input/output adapters to use said data transmission bus, wherein said transmission preventing means assigns one of said sets of range registers based on a grant signal from said arbiter.

5. The logically partitioned data processing system of claim 3 wherein said sets of range registers contain direct memory access addresses which limit operations that may be placed onto said data transmission bus by said input/output adapters.

6. The logically partitioned data processing system of claim 3 wherein said sets of range registers are programmable.

7. A method of preventing an operating system image within a logically partitioned data processing system from fetching or corrupting data from a memory location allocated to another operating system image within the data processing system, the method comprising the steps of:

receiving a request from the operating system image to access a given one of a plurality of input/output adapters each associated with a different one of a plurality of logical partitions of the data processing system, wherein the input/output adapters are connected to a single terminal bridge; and

accessing the given input/output adapter using memory mapped to the operating system image.

8. The method of claim 7 wherein said accessing step includes the steps of:

transmitting the request to a PCI host bridge using an input/output bus; and

conveying the request from the PCI host bridge to the terminal bridge using a PCI bus.

9. The method of claim 7 wherein said accessing step utilizes one of a plurality of sets of range registers of the terminal bridge, each associated with a respective one of the input/output adapters.

10. The method of claim 9 wherein said accessing step further utilizes an arbiter which selects one of the input/output adapters, to assign one of the sets of range registers based on a grant signal from the arbiter.

11. The method of claim 9 further comprising the step of associating each of the sets of range registers with direct memory access addresses which limit access by the input/output adapters.

12. The method of claim 9 further comprising the step of programmably loading the sets of range registers.

13. A computer program product for use in a data processing system for preventing an operating system image within a logically partitioned data processing system from fetching or corrupting data from a memory location allocated to another operating system image within the data processing system, the computer program product comprising:

a storage medium; and

program instructions stored on said storage medium for receiving a request from the operating system image to access a given one of a plurality of input/output adapters each associated with a different one of a plurality of logical partitions of the data processing system, wherein the input/output adapters are connected to a single terminal bridge, and for accessing the given input/output adapter using memory mapped to the operating system image.

14. The computer program product of claim 13 wherein the request comprises an input/output adapter identity, a memory address range to be mapped, and a direct memory access range, and said program instructions further determine that the identity of the input/output adapter, the memory address range, and the direct memory access range are allocated to the operating system image.

15. The computer program product of claim 13 wherein said program instructions access the input/output adapter utilizing one of a plurality of sets of range registers of the terminal bridge, each associated with a respective one of the input/output adapters.

16. The computer program product of claim 15 wherein said program instructions further load the sets of range registers.