Recording medium storing a program for constructing scan paths, scan path constructing method, and arithmetic processing system in which said scan paths are integrated

• US 20020010886A1
• Filed: 01/17/2001
• Published: 01/24/2002
• Est. Priority Date: 01/18/2000
• Status: Abandoned Application

• Current Assignee: Daihen Corporation, Roran Co.
• Original Assignee: Daihen Corporation
• Inventors: Tanaka, Ryohei, Nakao, Toshimitsu, Shigeki, Kenji
• Application Number:
  US09/764,499
• Publication Number:
  US 20020010886A1
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308
• CPC Class Codes: G01R 31/318591 Tools

Abstract

In a recording medium storing a scan path constructing program, a program makes a computer read in information about definition of scan paths, to thereby generate a logic of the scan paths at a hardware description language level as a basis of the scan paths constructed on an integrated circuit. This allows a user to easily construct the scan paths for registers and memories on the integrated circuit such as an FPGA based on the logic of the scan paths, thereby making it possible to improve the efficiency of a test for a user-created logic circuit structured on the integrated circuit, and shorten the developing time.

Claims

1. A recording medium storing a program for constructing scan paths on an integrated circuit by a computer, which are paths for inputting and outputting data to and from registers and memories on an integrated circuit such as an FPGA:

wherein the program makes the computer read in scan path defining information, and generate a logic of scan paths at hardware description language level as a basis for the scan paths to construct on the integrated circuit, based on the scan path defining information.

2. The recording medium storing a program for constructing scan paths according to claim 1,

wherein the program makes the computer further read describing information in a Backus Normal Form about a connecting relation between the generated logic of the scan paths, and logic of a controller for controlling the scan paths, and generate a connection file about the connecting relation at hardware description language level, based on the describing information.

3. A method of constructing scan paths by a computer, which are paths for inputting and outputting data to and from registers and memories on an integrated circuit such as an FPGA, comprising the steps of:

inputting defining information about the scan paths; and

generating a logic of scan paths at hardware description language level as a basis for the scan paths to construct on the integrated circuit, based on the scan path defining information.

4. The method of constructing scan paths according to claim 3, comprising steps of:

inputting describing information in a Backus Normal Form about a connecting relation between the generated logic of the scan paths and logic of a controller for controlling the scan paths; and

generating a connection file about the connecting relation at hardware description language level, based on the describing information.

5. An arithmetic processing system including an integrated circuit such as an FPGA, a computer and an interface device transmitting data between the integrated circuit and computer:

wherein the integrated circuit is provided with a data path for performing arithmetic processing in a predetermined data width, and a scan path for the data path while the computer is provided with a function for controlling the data path, to thereby transmit data between the computer and data path through the scan path and interface device.

6. An arithmetic processing system including plural integrated circuits each having a CPU core, a computer and an interface device transmitting data between the integrated circuits and computer:

wherein the arithmetic processing system constructs scan paths for each of CPU cores on plural integrated circuits; and

wherein the computer transmits code for controlling each of CPU cores on plural integrated circuits through the scan paths and interface device.