Semiconductor device and method for manufacturing the same

• US 20020011613A1
• Filed: 07/11/2001
• Published: 01/31/2002
• Est. Priority Date: 07/11/2000
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsuo, Kouji, Yagishita, Atsushi
• Application Number:
  US09/901,721
• Publication Number:
  US 20020011613A1
• Time in Patent Office: Days
• US Class Current: 257/284
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/095 the components being Schottky barrier gate field-effect transistors
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact

Abstract

There is disclosed a semiconductor device in which a device isolating insulating film is formed in a periphery of a device region of a semiconductor silicon substrate device region. A side wall insulating film formed of a silicon nitride film is formed to cover the periphery of a channel region on the silicon substrate. A Ta₂O₅ film, and a metal gate electrode are formed inside a trench whose side wall is formed of the side wall insulating film. An interlayer insulating film is formed on the device isolating insulating film. A Schottky source/drain formed of silicide is formed on the silicon substrate in a bottom portion of the trench whose side wall is formed of the side wall insulating film and interlayer insulating film. A source/drain electrode is formed on the Schottky source/drain.

Claims

1. A semiconductor device comprising:

a silicon substrate;

a gate insulating film formed on the silicon substrate;

a gate electrode formed on the gate insulating film; and

a source and a drain formed on said silicon substrate to hold the gate electrode therebetween, and formed of silicide to be Schottky junctioned to an interface with the silicon substrate,

wherein the semiconductor device satisfies at least one of conditions that a material of said gate insulating film is a highly dielectric film and that a material of said gate electrode is a metal.

2. The semiconductor device according to claim 1, wherein said silicon substrate is an SOI substrate.

3. The semiconductor device according to claim 1, wherein an extension region of a conductive type reverse to the conducive type of a channel region is formed in the semiconductor substrate between the channel region under said gate electrode and said source and drain.

4. The semiconductor device according to claim 1, wherein an impurity concentration of said extension region is higher than 0, and 3×

10¹⁹cm<sup>−

3</sup> or less.

5. A semiconductor device comprising nMISFET and pMISFET each comprising:

a silicon substrate;

a gate insulating film formed on the silicon substrate;

a gate electrode formed on the gate insulating film; and

source and drain formed on said silicon substrate to hold the gate electrode therebetween, and formed of silicide,

wherein the semiconductor device satisfies at least one of conditions that a material of said gate insulating film is a highly dielectric film and that a material of said gate electrode is a metal, and

silicide materials constituting said the nMISFET'"'"'s source and drain and pMISFET'"'"'s source and drain differ from each other.

6. The semiconductor device according to claim 5, wherein the silicide material constituting the source and drain of said pMISFET has a large work function for a channel of the pMISFET, and

the silicide material constituting the source and drain of said nMISFET has a small work function for the channel of the nMISFET.

7. The semiconductor device according to claim 5, wherein said silicon substrate is an SOI substrate.

8. The semiconductor device according to claim 5, wherein an extension region of a conductive type reverse to the conducive type of a channel region is formed in the semiconductor substrate between the channel region under said gate electrode and said source and drain.

9. The semiconductor device according to claim 8, wherein an impurity concentration of said extension region is higher than 0, and 3×

10¹⁹cm<sup>−

3</sup> or less.

10. A method for manufacturing a semiconductor device comprising the steps of:

forming an interlayer insulating film on a silicon substrate;

selectively removing said interlayer insulating film between source and drain forming regions of MISFET, to forming a gate trench;

forming a side wall insulating film on a side wall of said gate trench;

exposing said silicon substrate on a bottom surface of said gate trench, and forming a gate insulating film on the exposed surface of the silicon substrate;

burying/forming a gate electrode in said trench;

selectively etching said interlayer insulating film of the source and drain forming regions of said MISFET, to forming a source/drain trench with the surface of said silicon substrate exposed in a bottom portion thereof;

burying/forming a metal film in said source/drain trench, to forming a source electrode and a drain electrode; and

reacting said silicon substrate with said source electrode and the drain electrode, forming a silicide film to be Schottky junctioned to the silicon substrate, to forming a source and a drain.

forming a source and a drain which composed silicide films to be Schottky junctioned to the silicon substrate, the silicide film is formed by reacting said silicon substrate with said source electrode and the drain electrode.

11. The method for manufacturing the semiconductor device according to claim 10,

wherein said gate electrode and the gate insulating film are formed of a metal material and a highly dielectric material, and

said silicon substrate is reacted with said metal film at a temperature of 450°

or less.

12. A method for manufacturing a semiconductor device comprising the steps of:

forming an interlayer insulating film on a silicon substrate;

selectively removing said interlayer insulating film between source and drain forming regions of pMISFET and nMISFET, to forming a gate trench;

forming a side wall insulating film on a side wall of said gate trench;

exposing said silicon substrate on a bottom surface of said gate trench, and forming a gate insulating film on the exposed surface of the silicon substrate;

burying/forming a gate electrode in said gate trench;

removing said interlayer insulating film of the source and drain forming regions of the pMISFET, to forming a pMIS-side source/drain trench with the surface of said silicon substrate exposed in a bottom portion thereof;

burying/forming a first metal film in said pMIS-side source/drain trench, to forming a source electrode and a drain electrode of the pMISFET;

reacting said silicon substrate with the source electrode and the drain electrode of said pMISFET, forming a silicide film to be Schottky junctioned to the silicon substrate, and forming a source and a drain of the pMISFET;

forming a source and a drain of the pMISFET which composed silicide films to be Schottky junctioned to the silicon substrate, the silicide film is formed by reacting said silicon substrate with said source electrode and the drain electrode of the pMISFET;

removing said interlayer insulating film between source and drain forming regions of the nMISFET, to forming a nMIS-side source/drain trench with the surface of said silicon substrate exposed in a bottom portion thereof;

burying/forming a second metal film formed of a material different from the material of the first metal film in said nMIS-side source/drain trench, and forming a source electrode and a drain electrode of the nMISFET; and

reacting said silicon substrate with the source electrode and the drain electrode of the nMISFET, forming a silicide film to be Schottky junctioned to the silicon substrate, and forming a source and a drain of the nMISFET.

forming a source and a drain of the nMISFET which composed silicide films to be Schottky junctioned to the silicon substrate, the silicide film is formed by reacting said silicon substrate with said source electrode and the drain electrode of the nMISFET.

13. The method for manufacturing the semiconductor device according to claim 12,

wherein said gate electrode and the gate insulating film are formed of a metal material and a highly dielectric material, and

said silicon substrate is reacted with said metal film at a temperature of 450°

or less.

14. A method for manufacturing a semiconductor device comprising the steps of:

forming an extension region with a first conductive type impurity introduced therein on the surface of a silicon substrate;

forming an interlayer insulating film on said silicon substrate;

selectively removing said interlayer insulating film between source and drain forming regions of MISFET, to forming a gate trench;

forming a side wall insulating film on a side wall of said gate trench;

introducing a second conductive type impurity into the extension region of a lower portion of said gate trench, to forming a channel region;

exposing said silicon substrate on a bottom surface of said gate trench, and forming a gate insulating film on the exposed surface of the silicon substrate;

burying/forming a gate electrode in said gate trench;

selectively etching said interlayer insulating film of the source and drain forming regions of said MISFET, to forming a source/drain trench with the surface of said silicon substrate exposed in a bottom portion thereof;

burying/forming a metal film in said source/drain trench, to forming a source electrode and a drain electrode; and

reacting said silicon substrate with said source electrode and drain electrode, forming a silicide film to be Schottky junctioned to the silicon substrate, and forming a source and a drain.

forming a source and a drain which composed silicide films to be Schottky junctioned to the silicon substrate, the silicide film is formed by reacting said silicon substrate with said source electrode and the drain electrode.

15. The method for manufacturing the semiconductor device according to claim 14,

wherein said gate electrode and the gate insulating film are formed of a metal material and a highly dielectric material, and

said silicon substrate is reacted with said metal film at a temperature of 450°

or less.

16. A method for manufacturing a semiconductor device comprising the steps of:

forming an interlayer insulating film on a silicon substrate;

forming a source/drain trench with the surface of said silicon substrate exposed in a bottom portion thereof in said interlayer insulating film of MISFET source and drain forming regions;

burying/forming a metal film in said source/drain trench, and forming a source electrode and a drain electrode;

reacting said silicon substrate with the source electrode and the drain electrode, forming a silicide film to be Schottky junctioned to the silicon substrate, to forming a source and a drain;

forming a source and a drain of the nMISFET which composed silicide films to be Schottky junctioned to the silicon substrate, the silicide film is formed by reacting said silicon substrate with said source electrode and the drain electrode of the nMISFET;

forming a gate trench having an exposed side surface via which said source electrode is disposed opposite to the drain electrode;

forming a side wall insulating film in a side wall of said gate trench;

exposing said silicon substrate on a bottom surface of said gate trench, and forming a gate insulating film on the exposed surface of the silicon substrate; and

burying/forming a gate electrode in said gate trench.