Chip-like electronic components, a method of manufacturing the same, a pseudo wafer therefor and a method of manufacturing thereof

• US 20020011655A1
• Filed: 04/24/2001
• Published: 01/31/2002
• Est. Priority Date: 04/24/2000
• Status: Abandoned Application

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Ozaki, Hiroshi, Takaoka, Yuji, Nishiyama, Kazuo, Hirayama, Teruo
• Application Number:
  US09/841,582
• Publication Number:
  US 20020011655A1
• Time in Patent Office: Days
• US Class Current: 257/688
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05005 Structure
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1131 in liquid form
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A method of manufacturing the semiconductor chips comprises the steps of: pasting on a substrate an adhesive sheet having a property to retain its adhesive strength prior to a processing, then lose its adhesive strength after the processing; fixing a plurality of non-defective bare chips on this adhesive sheet, with their Al electrode pad surfaces facing down; coating a resin on a whole area other than the Al electrode pad surfaces of the plurality of non-defective bare chips including interspaces therebetween; applying a predetermined process to the adhesive sheet to weaken its adhesive strength of the adhesive sheet; peeling off a pseudo wafer bonding non-defective bare chips; and dicing the plurality of non-defective bare chips into a discrete non-defective electronic part by cutting the pseudo wafer at a position of the resin between respective non-defective bare chips.

Claims

1. A chip-like electronic component having at least its electrodes formed exclusively on one surface thereof, and surfaces other than said one surface are continuously covered with a protective material.

2. The chip-like electronic component according to claim 1 wherein said protective material comprises an organic insulating resin or an inorganic insulating material.

3. The chip-like electronic component according to claim 1, comprising a semiconductor chip diced from a wafer at a position of said protective material for mounting on a package substrate, wherein said electrode is formed on said one surface, which is a device surface, of said semiconductor chip, and both a side wall and a bottom surface of said semiconductor chip are covered with said protective material.

4. The chip-like electronic component according to claim 3 wherein a solder bump is formed on said electrode.

5. The chip-like electronic component according to claim 1 wherein a plurality and/or a plurality of different types of semiconductor chips are integrated as bonded by said protective material.

6. A pseudo wafer comprising a plurality and/or a plurality of different types of chip-like electronic components having at least their electrodes formed solely on one surface thereof, wherein interspaces between said plurality and/or said plurality of different types of chip-like electronic components and bottom surfaces thereof are continuously covered with said protective material, and bonded with each other.

7. The pseudo wafer according to claim 6 wherein said protective material comprises either one of an organic insulating resin and an inorganic insulating material.

8. The pseudo wafer according to claim 6 wherein said plurality and/or said plurality of different types of semiconductor chips arrayed thereon are diced at a position of said protective material between said plurality of semiconductor chips and fabricated into a discrete chip or an integrated semiconductor chip integrating a plurality and/or a plurality of different types of semiconductor chips to be mounted on a packaging substrate.

9. The pseudo wafer according to claim 8 wherein a solder bump is formed on said electrode.

10. A method of manufacturing a chip-like electronic component, comprising the steps of:

pasting an adhesive material on a substrate, said adhesive material having a property to retain an adhesive strength prior to a processing and to lose said adhesive strength after said processing;

fixing a plurality and/or a plurality of different types of semiconductor chips on said adhesive material with an electrode surface thereof facing down;

coating a whole area including said plurality and/or said plurality of different types of semiconductor chips and interspaces therebetween with a protective material;

applying a predetermined process to said adhesive material to weaken said adhesive strength of said adhesive material so as to peel off a pseudo wafer which bonds said plurality and/or said plurality of different types of semiconductor chips as covered with said protective material; and

dicing said plurality and/or said plurality of different types of semiconductor chips by cutting said protective material in said interspaces therebetween thereby obtaining a discrete semiconductor chip or a chip-like electronic component.

11. The method of manufacturing chip-like electronic components according to claim 10, wherein:

said substrate has a flat surface;

said adhesive material is an adhesive sheet;

said plurality and/or said plurality of different types of semiconductor chips are non-defective;

said protective material is either one of an organic insulating resin and an inorganic insulating material and is uniformly coated on said plurality of semiconductor chips from a bottom surface thereof to be hardened;

said predetermined process includes irradiating ultraviolet rays on said adhesive sheet through said flat substrate from a bottom surface thereof opposite to the surface bonding said plurality of semiconductor chips, or applying a chemical solution or heating the same to weaken said adhesive strength of said adhesive sheet so as to peel off a pseudo wafer having said plurality and/or said plurality of different types of semiconductor chips bonded thereon as covered with said protective material, from said flat substrate, thereby obtaining said pseudo wafer, wherein said plurality and/or said plurality of different types of semiconductor chips which are totally non-defective (conforming) are arrayed thereon with their electrode surfaces exposed; and

dicing said pseudo wafer between said plurality and/or said plurality of different types of semiconductor chips.

12. The method of manufacturing the chip-like electronic components according to claim 10, wherein:

said pseudo wafer is diced at a position of said protective material between said plurality and/or said plurality of different types of semiconductor chips; and

a discrete semiconductor chip or an integrated chip integrating a plural number and/or a plural different types of semiconductor chips to be mounted on a package substrate are obtained.

13. The method of manufacturing the chip-like electronic components according to claim 12, wherein a solder bump is on said electrodes.

14. The method of manufacturing the chip-like electronic components according to claim 10, wherein said plurality of semiconductor chips which are determined to be non-defective in a characteristic measurement thereof are fixed firmly on said substrate.

15. The method of manufacturing the chip-like electronic components according to claim 10, further comprising the steps of:

carrying out a characteristic measurement of said plurality of semiconductor chips in a state firmly fixed thereon and bonded with said protective material; and

selecting non-defective semiconductor chips or non-defective chip-like electronic components.

16. A method of manufacturing a pseudo wafer comprising the steps of:

pasting an adhesive material on a substrate, said material having a property to retain an adhesive strength prior to a processing and lose said adhesive strength after said processing;

fixing on said adhesive material a plurality and/or a plurality of different types of semiconductor chips with their electrode surfaces facing down;

coating with a protective material a whole area of said plurality and/or said plurality of different types of semiconductor chips including interspaces therebetween;

applying a predetermined process to said adhesive material so as to lose its adhesive strength; and

peeling off a pseudo wafer having said plurality and/or said plurality of different types of semiconductor chips fixed thereon.

17. The method of manufacturing said pseudo wafer according to claim 16, wherein:

said substrate has a flat surface;

said adhesive material is an adhesive;

said plurality and/or said plurality of different types of semiconductor chips are non-defective;

said protective material is either one of an organic insulating resin and an inorganic insulating material and in uniformly coated on said semiconductor chips from their bottom surfaces to be hardened;

said predetermined process includes irradiating ultraviolet rays, through said substrate, on said adhesive sheet from a bottom surface thereof opposite to the surface thereof fixing said plurality and/or said plurality of different types of semiconductor chips thereon, or applying a chemical solution thereto or heating said adhesive sheet to weaken the adhesive strength of said adhesive sheet so as to peel off a pseudo wafer having said plurality and/or said plurality of different types of semiconductor chips bonded with said protective material from said substrate; and

thereby

said pseudo wafer having said plurality and/or said plurality of different types of semiconductor chips which are non-defective, and arrayed thereon, with their electrode surfaces exposed is obtained.

18. The method of manufacturing the pseudo wafer according to claim 16, wherein a solder bump is formed on said electrode.

19. The method of manufacturing the pseudo wafer according to claim 16, wherein said semiconductor chips which are determined to be non-defective in characteristic measurements thereof is fixed on said substrate.

20. The method of manufacturing the pseudo wafer according to claim 16, further comprising the steps of:

carrying out characteristic measurements of said semiconductor chips in a state as bonded with said protective material; and

selecting non-defective semiconductor chips or non-defective chip-like electronic components.