Gigabit switch with fast filtering processor

• US 20020012585A1
• Filed: 06/11/2001
• Published: 01/31/2002
• Est. Priority Date: 06/09/2000
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kalkunte, Mohan, Ambe, Shekhar, Sampath, Srinivas
• Granted Patent: US 7,050,430 B2
• Time in Patent Office: Days
• US Class Current: 415/137
• CPC Class Codes: H04L 12/462 LAN interconnection over a bridge based backbone
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/16 Multipoint routing
• CPC Class Codes: H04L 45/245 Link aggregation, e.g. trunking
• CPC Class Codes: H04L 45/52 Multiprotocol routers
• CPC Class Codes: H04L 45/742 Route cache; Operation thereof
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/2458 Modification of priorities while in transit
• CPC Class Codes: H04L 47/266 Stopping or restarting the source, e.g. X-on or X-off
• CPC Class Codes: H04L 47/29 using a combination of thresholds
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 49/102 using shared medium, e.g. bus or ring
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/3036 Shared queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/352 Gigabit ethernet switching [GBPS]
• CPC Class Codes: H04L 49/354 for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/506 : Backpressure
• CPC Class Codes: H04L 49/508 : Head of Line Blocking Avoidance
• CPC Class Codes: H04L 49/602 : Multilayer or multiprotocol switching, e.g. IP switching
• CPC Class Codes: H04L 69/22 : Parsing or analysis of headers
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A network switch for network communications includes at least one data port interface supporting a plurality of data ports transmitting and receiving data. A CPU interface is configured to communicate with a CPU, and an internal memory communicates with the at least one data port interface. A memory management unit is provided for communicating data from at least one data port interface and the memory. A communication channel is provided, for communicating data and messaging information between the at least one data port interface, the memory, and the memory management unit. The configuration of the network switch also includes a fast filtering process, with the fast filtering processor filtering packets coming into the at least one data port interface. Selective filter action is taken based upon a filtering result.

Claims

1. A network switch for network communications, said network switch comprising:

at least one data port interface, said at least one data port interface supporting a plurality of data ports transmitting and receiving data;

a CPU interface, said CPU interface configured to communicate with a CPU;

a memory, said memory communicating with said at least one data port interface;

a memory management unit, said memory management unit including a memory interface for communicating data from said at least one data port interface and said memory;

a communication channel, said communication channel for communicating data and messaging information between said at least one data port interface, the CPU interface, said memory, and said memory management unit; and

a fast filtering processor, said fast filtering processor filtering packets coming into the at least one data port interface, and taking selective filter action on a particular packet of said packets based upon whether said particular packet is in-profile or out-profile.

2. A network switch as recited in claim 1, wherein said fast filtering processor is programmable by inputs from the CPU through the CPU interface.

3. A network switch as recited in claim 1, wherein one data port interface includes a rules table interface and a rules table thereupon, and wherein said fast filtering processor applies a filter mask to a packet incoming thereto, providing a filter result, and wherein said filter result is applied to predetermined rules in said rules table, and wherein action is taken on the packet based upon the filtering result.

4. A network switch as recited in claim 3, wherein said at least one data port interface, CPU interface, memory, memory management unit, communications channel, fast filtering processor, and said rules table are implemented on a common semiconductor substrate.

5. A network switch as recited in claim 4, wherein said fast filtering processor includes filter masks which filter ingress port fields, egress port fields, and filter select fields of an incoming packet.

6. A network switch as recited in claim 5, wherein the rules table includes filter value fields for filter result look-up, ingress port fields, egress port fields, filter select fields, action bit fields, priority bit fields, type-of-services fields, and output port fields.

7. A network switch as recited in claim 1, said fast filtering processor comprising a priority assignment unit for assigning a weighted priority value to untagged packets entering the at least one data port interface.

8. A network switch as recited in claim 1, wherein the fast filtering processor filters the packets independent of the CPU interface, and therefore without communicating with the CPU.

9. A network switch as recited in claim 1, wherein the fast filtering processor includes a tagging unit which applies an IEEE defined tag to incoming packets, said IEEE defined tag identifying packet parameters.

10. A network switch as recited in claim 9, wherein said packet parameters include class-of-service.

11. A method of handling data packets in a network switch, said method comprising:

placing incoming packets into an input queue;

applying the input data packets to an address resolution logic engine;

performing a lookup to determine whether certain packet fields are stored in a lookup table;

filtering the incoming packet through a fast filtering processor in order to determine whether the incoming packet is in-profile or out-profile and the type of filtering applied to the incoming packet based on whether the incoming packet is in-profile or out-profile;

discarding, forwarding, or modifying the packet based upon the filtering; and

if the packet is to be forwarded, applying a control message to the packet in order to control further packet forwarding,

wherein the packet data is placed on a first communication channel, and wherein is the control message is placed on a second communication channel, said first and second channels being separate but synchronized with each other.

12. A method as recited in claim 11, wherein filtering the incoming packet includes a step of tagging the incoming packet with an IEEE defined tag.

13. A method as recited in claim 12, wherein said IEEE defined tag defines packet parameters, including class-of-service priority.

14. A network switch for handling data packets comprising:

means for placing incoming packets into an input queue;

means for applying the input data packets to an address resolution logic engine;

means for performing a lookup to determine whether certain packet fields are stored in a lookup table;

means for filtering the incoming packet through a fast filtering processor in order to determine whether the incoming packet is in-profile or out-profile and the type of filtering applied to the incoming packet based on whether the incoming packet is in-profile or out-profile;

means for discarding, forwarding, or modifying the packet based upon the filtering; and

means for applying a control message to the packet in order to control further packet forwarding if the packet is to be forwarded,

wherein the packet data is placed on a first communication channel, and wherein the control message is placed on a second communication channel, said first and second channels being separate but synchronized with each other.

15. A method as recited in claim 14, wherein the means for filtering the incoming packet includes means for tagging the incoming packet with an IEEE defined tag.

16. A network switch as recited in claim 15, wherein said IEEE defined tag defines packet parameters, including class-of-service priority.