Composition for wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof

• US 20020013021A1
• Filed: 09/26/2001
• Published: 01/31/2002
• Est. Priority Date: 02/26/1997
• Status: Active Grant

• Current Assignee: TCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
• Original Assignee: Chang-Oh Jeong, Chi-Woo Kim, Chun-Gi You, Jang-Soo Kim, Mun-Pyo Hong, Myung-Koo Hur, Yang-Sun Kim, Young-Jae Tak
• Inventors: Hong, Mun-Pyo, You, Chun-Gi, Jeong, Chang-Oh, Kim, Jang-Soo, Hur, Myung-Koo, Kim, Chi-Woo, Kim, Yang-Sun, Tak, Young-Jae
• Granted Patent: US 6,582,982 B2
• Time in Patent Office: Days
• US Class Current: 438/149
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 23/4827 Materials
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The Mo or MoW composition layer has a low resistivity of less than 15 μΩcm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF₄+O₂ can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF₆+HCl (+He) or SF₆+Cl₂ (+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF₄, CHF₃, CHClF₂, CH₃F, and C₂F₆, yields good TFT characteristics, and H₂ plasma treatment can further improve the TFT characteristics.

Claims

1. A wiring for a display comprising a conductive layer having a dual-layered structure and tapered edges at an angle of 20˜

70 under the same etching condition.

2. The wiring for a display as claimed in claim 1, wherein the conductive layer comprises a lower layer having a resistivity less than 15 mWcm and an upper layer made of a pad material.

3. The wiring for a display as claimed in claim 2, wherein the lower layer is made of Al or Al alloy and the upper layer is made of a MoW alloy including tungsten of 0.01 atm % to 20 atm %, the rest of molybdenum and inevitable impurity.

4. The wiring for a display as claimed in claim 3, wherein the conductive layer is etched by wet etch using CH₃COOH/HNO₃/H₃PO₄/H₂O having HNO₃ of the concentration of 8-14%.

5. A manufacturing method of a wiring for a display comprising the steps of:

depositing a lower conductive layer on a substrate;

depositing an upper conductive layer having an etch rate larger than the etch rate of the lower conductive layer by 70-100 sec under a first etching condition on the lower conductive layer; and

etching simultaneously the upper conductive layer and the lower conductive layer under the first etching condition.

6. The manufacturing method as claimed in claim 5, wherein the lower conductive layer has a resistivity less than 15 mWcm and the upper conductive layer is made of a pad material.

7. The manufacturing method as claimed in claim 6, wherein the lower conductive layer comprises Al or Al alloy and the upper conductive layer comprises MoW alloy including tungsten of 0.01 atm % to 20 atm %, the rest of molybdenum and inevitable impurity.

8. The manufacturing method as claimed in claim 7, wherein the upper and the lower conductive layers are etched by using CH₃COOH/HNO₃/H₃PO₄/H₂O having HNO₃ of the concentration of 8˜

14%.

9. A wiring for a display comprising a conductive layer having a single-layered structure and made of molybdenum or molybdenum-tungsten alloy.

10. The wiring for a display as claimed in claim 9, further comprising a chromium layer formed under the conductive layer.

11. The wiring for a display as claimed in claim 9, wherein the molybdenum-tungsten alloy includes tungsten of 0.01 atm % to 20 atm %, the rest of molybdenum and inevitable impurity.

12. A manufacturing method of a TFT substrate for a display comprising the steps of:

depositing a MoW alloy layer including tungsten of 0.01 atm % to 20 atm %, the rest of molybdenum and inevitable impurity on a substrate;

forming a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line by patterning the MoW alloy layer using an etchant;

depositing a gate insulating layer;

forming an un-doped amorphous silicon layer and a doped amorphous silicon layer;

forming a data pattern including a data line, a source and a drain electrode, and a data pad connected to the data line;

etching the doped amorphous silicon layer using the data pattern as an etch mask;

depositing a passivation layer;

patterning the passivation layer along with the gate insulating layer to expose portions of the gate pad, the data pad and the drain electrode;

depositing a transparent conductive layer; and

etching the transparent conductive layer to form a gate conductive layer connected to the gate pad and a pixel electrode connected to the drain electrode.

13. The manufacturing method as claimed in claim 12, further comprising the steps of:

depositing a metal layer made of Al or Al alloy under the MoW alloy layer; and

etching the metal layer along with the MoW alloy layer by using the etchant.

14. The manufacturing method as claimed in claim 13, wherein the metal layer comprises an aluminum and a transition metal or a rare earth metal less than 5%.

15. The manufacturing method as claimed in claim 14, wherein the etchant is CH₃COOH/HNO₃/H₃PO₄/H₂O having HNO₃ of the concentration of 8-14%.

16. The manufacturing method as claimed in claim 15, wherein the data pattern comprises either a single layer of one selected from the group consisting of Cr, Mo or MoW alloy including tungsten, the rest of molybdenum and inevitable impurity, or a layer having a dual-layered structure of two selected from the group consisting of Cr, Mo or MoW alloy including tungsten, the rest of molybdenum and inevitable impurity.

17. The manufacturing method as claimed in claim 16, wherein the data pattern comprises a lower layer made of chromium and an upper layer made of a MoW alloy layer including tungsten of 0.01 atm % to 25 atm %, the rest of molybdenum and inevitable impurity, and the data pattern is etched by using HNO₃/(NH₄)₂Ce(NO₃)₆/H₂O.

18. The manufacturing method as claimed in claim 17, wherein the concentration of HNO₃ is 4-10% and the concentration of (NH₄)₂Ce(NO₃)₆ is 10-15%.

19. The manufacturing method as claimed in claim 16, wherein

the doped amorphous silicon layer is dry etched by using a gas consisting of a hydrogen halide and at least one selected from the group consisting of CF₄, CHF₃, CHClF₂, CH₃F and C₂F₆.

20. The manufacturing method as claimed in claim 16, wherein the data pattern is made of Mo or MoW, and patterning step comprises the steps of;

forming a photoresist pattern on the passivation layer, the photoresist pattern having openings at the positions corresponding to the gate pad, the data pad and the drain electrode,

exposing the data pad and the drain electrode under the condition of etch selectivity rate of the photoresist pattern to the insulating layer and the passivation layer in range of 1;

1 to 1;

1.5; and

exposing the gate pad under the condition of etch rate of the gate insulating layer and the passivation layer larger than 15 times than the etch rate of the data pattern.

21. The manufacturing method as claimed in claim 20, wherein either SF₆+HCl or SF₆+Cl₂ is used in the step of exposing the data pad and the drain electrode and CF₄+O₂ is used in the step of exposing the gate pad.

22. The manufacturing method as claimed in claim 16, wherein the data pattern is made of Mo or MoW, and patterning step comprises the steps of;

forming a photoresist pattern on the passivation layer, the photoresist pattern having openings at the positions corresponding to the gate pad, the data pad and the drain electrode,

exposing the data pad and the drain electrode;

forming a polymer layer on the substrate by reacting CF₄ and either H₂ or HCl in plasma; and

exposing the gate pad under the condition of etch rate of the gate insulating layer and the passivation layer larger than 15 times than the etch rate of the data pattern.

23. The manufacturing method of TFT substrate for the display as claimed in claim 22, wherein CF₄+O₂ is used in the step of exposing the gate pad and one selected from the group consisting of SF₆+HCl, SF₆+Cl₂ and CF₄+O₂ is used in the step of exposing the data pad and the drain electrode.

24. The manufacturing method as claimed in claim 16, wherein the data pattern is made of Mo or MoW, and patterning step comprises the steps of;

forming a photoresist pattern on the passivation layer, the photoresist pattern having openings at the positions corresponding to the gate pad, the data pad and the drain electrode,

exposing the data pad, the drain electrode and the gate pad by using the photoresist pattern as an etch mask and by using CF₄+O₂.

25. The manufacturing method as claimed in claim 24, wherein the proportion of O₂ to CF₄ is less than 4 to 10.

26. A manufacturing method of a TFT substrate for display comprises steps:

depositing a MoW alloy layer including tungsten of 0.01 atm % to 20 atm %, the rest of molybdenum and inevitable impurity on a substrate;

forming a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line by patterning the MoW alloy layer using an etchant and using a first mask;

depositing a gate insulating layer, an undoped amorphous silicon layer, a doped amorphous silicon layer, and a metal layer in sequence on the substrate;

etching sequentially the metal layer, the doped amorphous silicon layer and the undoped amorphous silicon layer using a second mask;

forming a pixel electrode having opening on the metal layer using a third mask;

forming a data line, a source and a drain electrode, and a contact layer by etching the metal layer and the doped amorphous silicon layer using the pixel electrode as a mask;

depositing a passivation layer; and

etching the passivation along with the gate insulating layer on the gate pad using a fourth mask.

27. The manufacturing method as claimed in claim 26, further comprising steps of:

depositing a metal layer made of Al or Al alloy under the MoW alloy layer; and

etching the metal layer along with the MoW alloy layer by using the etchant.

28. The manufacturing method as claimed in claim 27, wherein the metal layer comprises aluminum and a transition metal or a rare earth metal less than 5%.

29. The manufacturing method as claimed in claim 28, wherein the etchant is CH₃COOH/HNO₃/H₃PO₄/H₂O having HNO₃ of the concentration of 8-14%.

30. The manufacturing method as claimed in claim 29, wherein the data pattern comprises either a single layer of one selected from the group consisting of Cr, Mo or MoW alloy including tungsten, the rest of molybdenum and inevitable impurity, or a layer having a dual-layered structure of two selected from the group consisting of Cr, Mo or MoW alloy including tungsten, the rest of molybdenum and inevitable impurity.

31. The manufacturing method as claimed in claim 30, wherein the data pattern comprises a lower layer made of chromium and an upper layer made of a MoW alloy layer including tungsten of 0.01 atm % to 25 atm %, the rest of molybdenum and inevitable impurity, and the data pattern is etched by using HNO₃/(NH₄)₂Ce(NO₃)₆/H₂O.

32. The manufacturing method as claimed in claim 31, wherein the concentration of HNO₃ is 4-10% and the concentration of (NH₄)₂Ce(NO₃)₆ is 10-15%.

33. The manufacturing method as claimed in claim 30, wherein

the doped amorphous silicon layer is dry etched by using a gas consisting of a hydrogen halide and at least one selected from the group consisting of CF₄, CHF₃, CHClF₂, CH₃F and C₂F₆.

34. A thin film transistor substrate for a display comprising:

a transparent insulating substrate;

a gate pattern including a gate line, a gate electrode and a gate pad formed on the transparent substrate and made of a MoW alloy layer including tungsten of 0.01 atm % to 20 atm %, the rest of molybdenum and inevitable impurity;

a gate insulating layer covering the gate pattern;

an amorphous silicon layer on the gate insulating layer;

a data pattern including a data line, a data pad and a source and a drain electrode formed on the amorphous silicon layer;

a pixel electrode connected to the drain electrode.

35. The thin film transistor substrate as claimed in claim 34, further comprising a conductive layer made of Al or Al alloy under MoW alloy layer.

36. The thin film transistor substrate as claimed in claim 35, wherein the conductive layer comprises aluminum and either a transition metal or a rare earth metal less than 5%.

37. The thin film transistor substrate as claimed in claim 36, wherein the data pattern comprises either a single layer of one selected from the group consisting of Cr, Mo or MoW alloy including tungsten, the rest of molybdenum and inevitable impurity, or a layer having a dual-layered structure of two selected from the group consisting of Cr, Mo or MoW alloy including tungsten, the rest of molybdenum and inevitable impurity.

38. The thin film transistor substrate as claimed in claim 37, wherein the data pattern comprises a single layer of Mo or MoW alloy, the size of the substrate is larger than 370*470 mm².

39. The thin film transistor substrate as claimed in claim 38, wherein the thickness of the data pattern is in the range of 0.3-2.0 mm.

40. The thin film transistor substrate as claimed in claim 38, wherein the width of the data line is in the range of 3.0-10.0 mm.

41. A gas for dry etch of an amorphous silicon layer comprising a hydrogen halide and at least one selected from the group consisting of CF₄, CHF₃, CHClF₂, CH₃F and C₂F₆.

42. A manufacturing method of display comprising steps:

forming a doped amorphous silicon layer on a substrate;

forming a first and a second electrode made of Mo or MoW alloy;

dry etching the doped amorphous silicon layer by using a gas consisting of a hydrogen halide and at least one selected from the group consisting of CF₄, CHF₃, CHClF₂, CH₃F and C₂F₆ and using the first and the second electrode as an etch mask.