High voltage device having polysilicon region in trench and fabricating method thereof

• US 20020013029A1
• Filed: 05/24/2001
• Published: 01/31/2002
• Est. Priority Date: 07/28/2000
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Hwang, Lee-Yeun
• Granted Patent: US 6,706,567 B2
• Time in Patent Office: Days
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A high voltage device prevents or minimizes the lowering of a maximum operating voltage range. Bulk resistances of the drift regions are reduced by forming trenches within the drift regions and filling the trenches with conductive polysilicon layers. The polysilicon layers reduce the bulk resistances and prevents or minimizes the operation of parasitic bipolar junction transistors typically formed when the high voltage device is manufactured.

Claims

1. A high voltage device, comprising:

an N-type drift region and a P-type drift region formed on a substrate;

a gate region defined at an intersection between the N and P-type drift region, the gate region having an oxide film deposited on an upper portion of the gate region and a gate electrode formed on the oxide film;

a source region being defined in one of the N and P-type drift regions, the source region having a first trench filled with a first polysilicon layer, a first high density diffusion layer formed on an upper portion of the first polysilicon layer and a source electrode formed on the high density diffusion layer; and

a drain region being defined in the other of the N and P-type drift regions, the drain region having a second high density diffusion layer formed on an upper portion of the drain region and a drain electrode formed on the second high density diffusion layer.

2. The high voltage device according to claim 1, further comprising:

a second polysilicon layer filling a second trench formed between the N and P-type drift regions of the gate region such that the oxide film is deposited in the second trench as well as the upper portion of the drift region corresponding to the drain region.

3. The high voltage device according to claim 1, wherein the first polysilicon is formed in the first trench such that a depth of the first trench is substantially equal to a depth of the one of the N and P-type drift region where the source region is defined.

4. The high voltage device according to claim 1, wherein the first trench is formed at the P-type drift region.

5. The high voltage device according to claim 4, wherein the first high density diffusion layer is an N⁺ layer.

6. The high voltage device according to claim 5, wherein the second high density diffusion layer is an N⁺ layer.

7. The high voltage device according to claim 5, further comprising:

a third high density diffusion layer in the source region adjacent to the first high density layer.

8. The high voltage device according to claim 7, wherein the third high density diffusion layer is a P⁺ layer.

9. A method for fabricating a high voltage device, comprising:

forming an N-type drift region and a P-type drift region on a substrate;

forming a first trench in a source region, the source region being defined in one of the N and P-type drift regions;

forming a first polysilicon layer filling the first trench;

forming a first high density diffusion layer on a first upper portion of the first polysilicon layer and on an upper portion of the one of the N and P-type drift region adjacent to the first trench;

depositing an oxide film on an upper portion of a gate region, the gate region being defined near an intersection between the N and P-type drift regions and occupying portions of the N and P-type drift regions;

forming a gate electrode on the oxide film; and

forming a metal electrode on the first high density diffusion layer.

10. The method according to claim 9, wherein in the step of forming the first trench, a second trench is formed in the gate region.

11. The method according to claim 9, wherein the first polysilicon layer is formed in the first trench, and the first trench has a depth that is substantially equal to a depth of the one of the N and P-type drift region where the source region is defined.

12. The method according to claim 9, wherein the first trench is formed at the P-type drift region.

13. The method according to claim 12, wherein the first high density diffusion layer is an N⁺ layer.

14. The method according to claim 13, wherein the second high density diffusion layer is an N⁺ layer.

15. The method according to claim 13, further comprising:

a third high density diffusion layer in the source region adjacent to the first high density layer.

16. The method according to claim 15, wherein the third high density diffusion layer is a P⁺ layer.

17. A high voltage device, comprising:

a substrate;

a first drift region and a second drift region formed in the substrate;

a gate electrode formed over a gate region, the gate region being defined over an intersection of said first and second drift regions such that said gate region includes a part of said first drift region and a part of said second drift region;

a first polysilicon layer filling a first trench formed in a source region, the source region being defined in said first drift region;

a first high density diffusion layer formed in an upper portion of the source region including a portion of the first polysilicon layer and a portion of the first drift region in between the first trench and the gate region; and

a second high density diffusion layer formed in a drain region, the drain region being defined in the second drift region.

18. The high voltage device of claim 17, wherein the first drift region is of P-type and the second drift region is of N-type.

19. The high voltage device of claim 17, wherein the first high density diffusion layer is of N⁺ type.

20. The high voltage device of claim 19, wherein the second high density diffusion layer is of N⁺ type.

21. The high voltage device of claim 17, further including:

a third high density diffusion layer formed in another portion of the source region adjacent to the first high density diffusion layer.

22. The high voltage device of claim 21, wherein the third high density diffusion layer is of P⁺ type.

23. The high voltage device of claim 17, further including:

an oxide film formed in a second trench formed in the gate region, the oxide film also formed on an upper portion of the gate region in between the second trench and the drain region; and

a second polysilicon layer filling the second trench covering the oxide film formed within the second trench such that the gate electrode covers at least a portion of the second polysilicon layer and the oxide film on the upper portion of the gate region.

24. A method for forming a high voltage device, comprising:

forming a first drift region and a second drift region in a substrate;

forming a gate electrode over a gate region, the gate region being defined over an intersection of said first and second drift regions such that said gate region includes a part of said first drift region and a part of said second drift region;

forming a first trench in a source region, the source region being defined in said first drift region;

filling the first trench with a first polysilicon layer;

forming a first high density diffusion layer in an upper portion of the source region including a portion of the first polysilicon layer and a portion of the first drift region in between the first trench and the gate region; and

forming a second high density diffusion layer in a drain region, the drain region being defined in the second drift region.

25. The method of claim 24, wherein the first drift region is of P-type and the second drift region is of N-type.

26. The method of claim 24, wherein the first high density diffusion layer is of N⁺ type.

27. The method of claim 26, wherein the second high density diffusion layer is also of N⁺ type.

28. The method of claim 24, further forming a third high density diffusion layer in another portion of the source region adjacent to the first high density diffusion layer.

29. The method of claim 28, wherein the third high density diffusion layer is of P⁺ type.

30. The method of claim 24, further including:

forming a second trench in the gate region,

forming an oxide film in the trench and on an upper portion of the gate region in between the second trench and the drain region; and

filling the second trench with a second polysilicon layer covering the oxide film formed within the second trench such that the gate electrode covers at least a portion of the second polysilicon layer and the oxide film on the upper portion of the gate region.