Semiconductor device, function setting method thereof, and evaluation method thereof

• US 20020014699A1
• Filed: 10/03/2001
• Published: 02/07/2002
• Est. Priority Date: 10/05/2000
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Shiomi, Kentaro, Yokoyama, Toshiyuki, Motohara, Akira, Fujimura, Katsuya
• Granted Patent: US 7,148,503 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.

Claims

1. A semiconductor device, comprising:

a semiconductor circuit board having a wiring layer; and

a plurality of evaluation chip IPs that are mounted by lamination on the semiconductor circuit board, and that each have at least one function.

2. The semiconductor device in accordance with claim 1,

wherein the wiring layer of the semiconductor circuit board comprises a normal operation wiring layer and an evaluation wiring layer provided above the normal operation wiring layer;

and

wherein the evaluation chip IPs are electrically connected to at least the evaluation wiring layer.

3. A semiconductor device, comprising:

a semiconductor circuit board having a wiring layer;

a plurality of chip IPs that are mounted by lamination on the semiconductor circuit board, and that each have a plurality of functions; and

a function selection means for activating only a portion of the plurality of functions of the plurality of chip IPs.

4. The semiconductor device in accordance with claim 3,

wherein the function selection means is a logic signal applied to the plurality of functions.

5. The semiconductor device in accordance with claim 3,

wherein the function selection means is a selector that is connected to the plurality of functions, receives a logic input, and outputs only said portion of functions.

6. The semiconductor device in accordance with claim 5,

wherein said wiring layer is provided with a power source wiring for supplying a power source voltage, and a ground wiring for supplying a ground voltage;

wherein the semiconductor device further comprises a connection means for connecting either the power source wiring or the ground wiring of the semiconductor wiring layer to the selector; and

wherein the logic input is the power source voltage or the ground voltage.

7. The semiconductor device in accordance with claim 3,

wherein the function selection means is a connection means for connecting said portion of functions to the wiring layer of the semiconductor circuit board.

8. The semiconductor device in accordance with claim 3,

further comprising a chip IP that is provided on the semiconductor circuit board, that is connected via the wiring layer to the plurality of functions of the plurality of chip IPs, and that has a control circuit that performs control such that only said portion of functions is selected.

9. The semiconductor device in accordance with claim 3,

further comprising a storage means for storing which of the plurality of functions are to be activated or which are not to be activated, the storage means being connected to the plurality of functions of the plurality of chip IPs;

and

a setting means for setting the storage in the storage means such that only said portion of functions are activated.

10. The semiconductor device in accordance with claim 9,

wherein the setting means is connected to the storage means over a network.

11. A semiconductor device, comprising:

a semiconductor circuit board having a wiring layer;

a chip IP that is mounted by lamination on the semiconductor circuit board, and that has a plurality of functions; and

a function information storage means for storing function information related to said plurality of functions, the function information storage means being provided in the chip IP.

12. The semiconductor device in accordance with claim 11,

wherein the function information storage means stores function information by associating said functions with ID numbers.

13. The semiconductor device in accordance with claim 11,

wherein the function information related to said plurality of functions is formatted so that it can be displayed on a display means.

14. The semiconductor device in accordance with claim 11,

further comprising another chip IP that is configured so as to determine its own function by receiving said function information of said chip IP.

15. The semiconductor device in accordance with claim 11,

wherein the chip IP is configured to output the function information stored in the function information storage means when receiving a key signal.

16. The semiconductor device in accordance with claim 11,

further comprising an encryption means for encrypting the function information outputted by the function information storage means.

17. The semiconductor device in accordance with claim 16,

further comprising a decryption means for decrypting and outputting said encrypted function information when a key signal has been received.

19. The semiconductor device in accordance with claim 18,

wherein the plurality of chip IPs are each provided with a key signal communication portion for sending and receiving a key signal, and the chip IPs are configured so that they output the function information stored in the function information storage means when their own key signal communication portion has received the key signal.

20. The semiconductor device in accordance with claim 19,

wherein the plurality of chip IPs are configured so as to perform the communication of the function information after the function information of the function information storage means has been decoded into a code that can be mutually recognized.

21. The semiconductor device in accordance with claim 18,

wherein the function information storage means store the function information by associating said functions with ID numbers;

and

wherein the semiconductor device further comprises a function recognition means for recognizing the function information based on its ID number.

22. The semiconductor device in accordance with claim 21,

wherein the function recognition means is provided in a chip IP separate to the aforementioned chip IPs.

23. The semiconductor device in accordance with claim 22,

wherein the function recognition means is provided as storage content of a memory.

24. The semiconductor device in accordance with claim 21,

wherein the function recognition means is provided in one piece with the function information storage means in the chip IPs.

25. The semiconductor device in accordance with claim 21,

wherein the function information storage means comprise a first storage portion storing the lower n bits of an m bit address (with n<

m) used in the semiconductor device, and a second storage portion storing the upper bits from (n+1) upward of the m bit address as said ID number; and

wherein the semiconductor device further comprises a means for judging whether the upper bits from (n +1) upward of the m bit input address match with the ID number of the second storage portion.

26. The semiconductor device in accordance with claim 19,

wherein the plurality of chip IPs are configured such that they can change or set their own functions based on function information of function information storage means in the other chip IPs.

27. The semiconductor device in accordance with claim 26,

further comprising a control circuit that changes or sets the function of the chip IPs upon receiving storage information of the function information storage means in the chip IPs.

30. The method for evaluating a semiconductor device according to claim 29,

wherein step (b) is performed by displaying internal documentation storing the function of the chip IPs on a display device.

31. The method for evaluating a semiconductor device according to claim 29,

wherein in step (a), the wiring layer of the semiconductor wiring circuit is formed separated into a normal operation wiring layer and an evaluation wiring layer above the normal operation wiring layer;

and

the method further includes a step of removing the evaluation wiring layer from the semiconductor circuit board and leaving the normal operation wiring layer, which is performed after step (b).

18. A semiconductor device, comprising:

a semiconductor circuit board having a wiring layer;

a plurality of chip IPs that are mounted by lamination on the semiconductor circuit board, and that each have a plurality of functions; and

a function information storage means for storing information related to said plurality of functions, the function information storage means being provided in the chip IPs;

wherein the plurality of chip IPs are configured so that they can read out function information by accessing the function information storage means of other chip IPs.

28. A semiconductor device, comprising:

a semiconductor circuit board having a wiring layer;

a plurality of chip IPs that are mounted by lamination on the semiconductor circuit board; and

a bus chip IP comprising a bus that connects the chip IPs to one another.

29. A method for evaluating a semiconductor device, comprising:

a step (a) of mounting, by lamination on a semiconductor circuit board having a wiring layer, a plurality of evaluation chip IPs each having at least one function; and

a step (b) of evaluating said at least one function of the evaluation chips by simulation.

32. A method for evaluating a semiconductor device comprising a semiconductor circuit board having a wiring layer, and a plurality of chip IPs that are mounted by lamination on the semiconductor circuit board;

wherein a connection test is performed by exchanging information between corresponding terminals among the plurality of chip IPs.

33. A method for function setting of a semiconductor device comprising a semiconductor circuit board having a wiring layer, and a chip IP that is mounted by lamination on the semiconductor circuit board and that has a plurality of functions;

wherein settings are performed such that only a portion of the plurality of functions are activated.

34. The method for function setting of a semiconductor device in accordance with claim 33,

wherein only said portion of functions is activated by locking a wiring layout of the wiring layer.

35. The method for function setting of a semiconductor device in accordance with claim 34,

wherein only said portion of functions is activated by locking a logic input supplied to the plurality of functions.

36. The method for function setting of a semiconductor device in accordance with claim 33,

wherein only said portion of functions is activated by allowing only said portion of functions to be read out.

37. The method for function setting of a semiconductor device in accordance with claim 33,

wherein only said portion of functions is activated by remote control over a network.

38. The method for function setting of a semiconductor device in accordance with claim 33,

wherein only said portion of functions is activated by inputting a clock signal only into said portion of functions.

39. The method for function setting of a semiconductor device in accordance with claim 33,

wherein only said portion of functions is activated by supplying a power source voltage only to said portion of functions.

40. The method for function setting of a semiconductor device in accordance with claim 33,

wherein only said portion of functions is activated by supplying an input signal only to said portion of functions.

41. A method for function setting of a semiconductor device comprising a semiconductor circuit board having a wiring layer, and a plurality of chip IPs that are mounted by lamination on the semiconductor circuit board;

wherein, in accordance with function information of only a portion of the plurality of chip IPs, the functions of the other chip IPs are changed or set.

42. A method for function setting of a semiconductor device comprising a semiconductor circuit board having a wiring layer, a plurality of chip IPs that are mounted by lamination on the semiconductor circuit board and that each have a plurality of functions, and function information storage means provided on each of the chip IPs that is for storing function information relating to said plurality of functions;

wherein, based on the function information of only a portion of the plurality of chip IPs, the functions of the other chip IPs are changed or set.