Driver circuit of a display device

• US 20020015032A1
• Filed: 07/25/2001
• Published: 02/07/2002
• Est. Priority Date: 07/25/2000
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Tanada, Yoshifumi, Koyama, Jun
• Granted Patent: US 6,760,005 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G09G 2300/0417 Special arrangements specific to the use of low carrier mobility technology
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0294 Details of sampling or holding circuits arranged for use in a driver for data electrodes
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

In a driver circuit of a display device handling a digital image signal, there is provided a driver circuit with a structure in which the timing of holding the image signal in a latch circuit is not influenced by a delay of a sampling pulse. A pre-charge TFT (102) is turned ON in a return line period and an input terminal of a holding portion (101) is set as Hi (VDD). When there is input to all the three signals, the sampling pulse, and a multiplex signal and the digital image signal which are input from the outside, TFTs (104 to 106) all turn ON, and the potential of the input terminal of the holding portion (101) becomes a Lo potential. Thus, holding of the digital image signal is performed. A sampling pulse width is wider than a pulse width of the two signals input from the outside, and the output periods of the two signals input from the outside are completely included in an output period of the sampling pulse. Thus, even if a slight delay is generated, there is no influence on the holding timing, and the holding timing may be easily determined.

Claims

1. A driver circuit of a display device comprising:

a holding circuit performing holding of a digital image signal which is input;

a pre-charge circuit provided between a signal input portion of the holding circuit and a first power supply; and

a holding operation selection circuit provided between the signal input portion of the holding circuit and a digital image signal line,

wherein the pre-charge circuit is input with a pre-charge signal, and

wherein the holding operation selection circuit is input with a sampling pulse, a multiplex signal and a digital image signal.

2. A circuit according to claim 1, wherein the multiplex signal and the digital image signal are both directly input from the outside.

3. A circuit according to claim 1, wherein a pulse width of the digital image signal and the pulse width of the multiplex signal are both smaller than the pulse width of the sampling pulse.

4. A circuit according to claim 1, wherein the holding of the potential in the holding circuit is performed by the holding circuit formed of two inverters provided in a loop shape.

5. A circuit according to claim 1, wherein the holding of the potential in the holding circuit is performed by a holding capacity.

6. A display device using a circuit according to claim 1.

7. A television using the display device according to claim 6.

8. A personal computer using the display device according to claim 6.

9. A portable terminal using the display device according to claim 6.

10. A video camera using the display device according to claim 6.

11. A projector using the display device according to claim 6.

13. A circuit according to claim 12, wherein the multiplex signal and the digital image signal are both directly input from the outside.

14. A circuit according to claim 12, wherein a pulse width of the digital image signal and the pulse width of the multiplex signal are both smaller than the pulse width of the sampling pulse.

15. A circuit according to claim 12, wherein the holding of the potential in the holding circuit is performed by the holding circuit formed of two inverters provided in a loop shape.

16. A circuit according to claim 12, wherein the holding of the potential in the holding circuit is performed by a holding capacity.

17. A display device using a circuit according to claim 12.

18. A television using the display device according to claim 17.

19. A personal computer using the display device according to claim 17.

20. A portable terminal using the display device according to claim 17.

21. A video camera using the display device according to claim 17.

22. A projector using the display device according to claim 17.

24. A circuit according to claim 23,

wherein the first transistor is in continuity by the input of the pre-charge signal, and a potential of the signal input portion of the holding circuit takes a first power supply potential,

wherein the multiplex signal and the digital image signal are input during the period that the sampling pulse is output, the second to fourth transistors are in continuity, and the potential in the signal input portion of the holding circuit changes to a second power supply potential, and

wherein thereafter, until the next return line period, the second power supply potential is held in the holding circuit.

25. A circuit according to claim 23, wherein the multiplex signal and the digital image signal are both directly input from the outside.

26. A circuit according to claim 23, wherein a pulse width of the digital image signal and the pulse width of the multiplex signal are both smaller than the pulse width of the sampling pulse.

27. A circuit according to claim 23, wherein the holding of the potential in the holding circuit is performed by the holding circuit formed of two inverters provided in a loop shape.

28. A circuit according to claim 23, wherein the holding of the potential in the holding circuit is performed by a holding capacity.

29. A display device using a circuit according to claim 23.

30. A television using the display device according to claim 29.

31. A personal computer using the display device according to claim 29.

32. A portable terminal using the display device according to claim 29.

33. A video camera using the display device according to claim 29.

34. A projector using the display device according to claim 29.

36. A circuit according to claim 35,

wherein the first transistor is in continuity by the input of the pre-charge signal, and a potential of the signal input portion of the holding circuit takes a first power supply potential,

wherein the multiplex signal and the digital image signal are input during the period that the sampling pulse is output, the second to fourth transistors are in continuity, and the potential in the signal input portion of the holding circuit changes to a second power supply potential, and

wherein thereafter, until the next return line period, the second power supply potential is held in the holding circuit.

37. A circuit according to claim 35, wherein the multiplex signal and the digital image signal are both directly input from the outside.

38. A circuit according to claim 35, wherein a pulse width of the digital image signal and the pulse width of the multiplex signal are both smaller than the pulse width of the sampling pulse.

39. A circuit according to claim 35, wherein the holding of the potential in the holding circuit is performed by the holding circuit formed of two inverters provided in a loop shape.

40. A circuit according to claim 35, wherein the holding of the potential in the holding circuit is performed by a holding capacity.

41. A display device using a circuit according to claim 40.

42. A television using the display device according to claim 40.

43. A personal computer using the display device according to claim 40.

44. A portable terminal using the display device according to claim 40.

45. A video camera using the display device according to claim 40.

46. A projector using the display device according to claim 40.

48. A circuit according to claim 47, wherein:

the first transistor is in continuity by the input of the pre-charge signal, the potential in the signal input portion of the holding circuit takes a first power supply potential;

the multiplex signal and the digital image signal are input during the period that the sampling pulse is output, the third to fifth transistors are in continuity, and the potential in the signal input portion of the holding circuit changes to the second power supply potential; and

thereafter, until the next return line period, the second power supply potential is held in the holding circuit.

49. A circuit according to claim 47, wherein the multiplex signal and the digital image signal are both directly input from the outside.

50. A circuit according to claim 47, wherein a pulse width of the digital image signal and the pulse width of the multiplex signal are both smaller than the pulse width of the sampling pulse.

51. A circuit according to claim 47, wherein the holding of the potential in the holding circuit is performed by the holding circuit formed of two inverters provided in a loop shape.

52. A circuit according to claim 47, wherein the holding of the potential in the holding circuit is performed by a holding capacity.

53. A display device using a circuit according to claim 47.

54. A television using the display device according to claim 53.

55. A personal computer using the display device according to claim 53.

56. A portable terminal using the display device according to claim 53.

57. A video camera using the display device according to claim 53.

58. A projector using the display device according to claim 53.

60. A circuit according to claim 59, wherein:

the first transistor is in continuity by the input of the pre-charge signal, the potential in the signal input portion of the holding circuit takes a first power supply potential;

the multiplex signal and the digital image signal are input during the period that the sampling pulse is output, the third to fifth transistors are in continuity, and the potential in the signal input portion of the holding circuit changes to the second power supply potential; and

thereafter, until the next return line period, the second power supply potential is held in the holding circuit.

61. A circuit according to claim 59, wherein the multiplex signal and the digital image signal are both directly input from the outside.

62. A circuit according to claim 59, wherein a pulse width of the digital image signal and the pulse width of the multiplex signal are both smaller than the pulse width of the sampling pulse.

63. A circuit according to claim 59, wherein the holding of the potential in the holding circuit is performed by the holding circuit formed of two inverters provided in a loop shape.

64. A circuit according to claim 59, wherein the holding of the potential in the holding circuit is performed by a holding capacity.

65. A display device using a circuit according to claim 59.

66. A television using the display device according to claim 65.

67. A personal computer using the display device according to claim 65.

68. A portable terminal using the display device according to claim 65.

69. A video camera using the display device according to claim 65.

70. A projector using the display device according to claim 65.

12. A driver circuit of a display device comprising:

a holding circuit performing holding of a digital image signal which is input;

a pre-charge circuit provided between a signal input portion of the holding circuit and a first power supply; and

a holding operation selection circuit provided between the signal input portion of the holding circuit and a digital image signal line,

wherein the pre-charge circuit is input with a pre-charge signal;

wherein the holding operation selection circuit is input with a sampling pulse, a multiplex signal and a digital image signal,

wherein the pre-charge circuit, by the input of the pre-charge signal, makes the signal input portion of the holding portion and the first power supply in continuity, and

wherein in the holding operation selection circuit, holding of the digital image signal is performed in the holding circuit, in a period where the input of the sampling pulse, the multiplex signal and the digital image signal overlap.

23. A driver circuit of a display device comprising:

a holding circuit performing holding of a digital image signal which is input;

a first transistor provided between a first power supply and a signal input portion of the holding circuit; and

second, third and fourth transistors provided serially between a second power supply and the signal input portion of the holding circuit, wherein

wherein a gate electrode of the first transistor is input with a pre-charge signal, a gate electrode of the second transistor is input with a multiplex signal, a gate electrode of the third transistor is input with a digital image signal, and a gate electrode of the fourth transistor is input with a sampling pulse.

35. A driver circuit of a display device comprising:

a holding circuit performing holding of a digital image signal which is input;

a first transistor provided between a first power supply and a signal input portion of the holding circuit;

second, third and fourth transistors provided serially between a second power supply and the signal input portion of the holding circuit,

wherein a gate electrode of the first transistor is input with a pre-charge signal, a gate electrode of the second transistor is input with a multiplex signal, a gate electrode of the third transistor is input with a digital image signal, and a gate electrode of the fourth transistor is input with a sampling pulse; and

wherein the holding circuit performs holding of the digital image signal in a period where the input of the multiplex signal, the digital image signal and the sampling pulse overlap.

47. A driver circuit of a display device, comprising:

a holding circuit performing holding of a digital image signal which is input;

first and second transistors arranged in parallel between a first power supply and a signal input portion of the holding circuit; and

third, fourth and fifth transistors arranged serially between a second power supply and the signal input portion of the holding circuit, wherein

a gate electrode of the first transistor is input with a pre-charge signal;

a gate electrode of the second transistor is applied with a second power supply potential;

a gate electrode of the third transistor is input with a multiplex signal;

a gate electrode of the fourth transistor is input with a digital image signal; and

a gate electrode of the fifth transistor is input with a sampling pulse.

59. A driver circuit of a display device, comprising:

a holding circuit performing holding of a digital image signal which is input;

first and second transistors arranged in parallel between a first power supply and a signal input portion of the holding circuit;

third, fourth and fifth transistors arranged serially between a second power supply and the signal input portion of the holding circuit, wherein;

a gate electrode of the first transistor is input with a pre-charge signal;

a gate electrode of the second transistor is applied with a second power supply potential;

a gate electrode of the third transistor is input with a multiplex signal;

a gate electrode of the fourth transistor is input with a digital image signal;

a gate electrode of the fifth transistor is input with a sampling pulse; and

a holding circuit performs holding of the digital image signal in a period where the input of the multiplex signal, the digital image signal and the sampling pulse overlap.

71. A driver circuit of a display device comprising:

a holding circuit performing holding of a digital image signal which is input;

a NAND circuit; and

an analog switch, wherein

the NAND circuit is input with a sampling pulse and a multiplex signal;

the holding circuit is input with a digital image signal through the analog switch;

the continuity and non-continuity of the analog switch is controlled by an output of the NAND circuit;

a write in of the image signal to the holding circuit is performed with the continuity of the analog switch; and

thereafter, until the next return line period, the image signal is held in the holding circuit.

72. A circuit according to claim 71, wherein the multiplex signal and the digital image signal are both directly input from the outside.

73. A circuit according to claim 71, wherein a pulse width of the digital image signal and the pulse width of the multiplex signal are both smaller than the pulse width of the sampling pulse.

74. A circuit according to claim 71, wherein the holding of the potential in the holding circuit is performed by the holding circuit formed of two inverters provided in a loop shape.

75. A circuit according to claim 71, wherein the holding of the potential in the holding circuit is performed by a holding capacity.

76. A display device using a circuit according to claim 71.

77. A television using the display device according to claim 76.

78. A personal computer using the display device according to claim 76.

79. A portable terminal using the display device according to claim 76.

80. A video camera using the display device according to claim 76.

81. A projector using the display device according to claim 76.