Low voltage flash EEPROM memory cell with improved data retention

• US 20020015327A1
• Filed: 09/20/2001
• Published: 02/07/2002
• Est. Priority Date: 05/09/2000
• Status: Active Grant

• Current Assignee: Broadcom International Pte Ltd. (Broadcom, Inc.)
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Singh, Ranbir, McPartland, Richard J.
• Granted Patent: US 6,552,931 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The present invention provides memory circuit including a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.

Claims

1. A memory cell, comprising:

a control input;

a switch; and

a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.

2. The memory cell as recited in claim 1 further comprising an erase input that is electrically connected to the switch.

3. The memory cell as recited in claim 1 wherein the voltage transfer structure further comprises a non-linear capacitor connected in series with the control input and the switch and in parallel with the linear capacitor.

4. The memory cell as recited in claim 3 wherein the non-linear capacitor forms a portion of the linear capacitor.

5. The memory cell as recited in claim 1 wherein the linear capacitor has an overlap capacitance substantially greater than a capacitance of the switch.

6. The memory cell as recited in claim 5 wherein the linear capacitor has a first electrode and the linear capacitor includes source and drain regions, a gate dielectric located over the source and drain regions, and a serpentine second electrode located on the gate dielectric that overlaps the source and drain regions and the first electrode.

7. The memory cell as recited in claim 6 wherein the second electrode forms a floating gate for the memory cell.

8. The memory cell as recited in claim 1 further including a gate oxide having a thickness of about 10 nm.

9. A method of fabricating a memory cell, comprising

forming a control input;

forming a switch; and

forming a voltage transfer structure, including;

forming a linear capacitor that electrically couples the control input to the switch.

10. The method as recited in claim 9 further comprising forming an erase input that is electrically connected to the switch.

11. The method as recited in claim 9 further comprising forming a non-linear capacitor in series with the control input and the switch and in parallel with the linear capacitor.

12. The method as recited in claim 11 wherein forming the non-linear capacitor includes forming a portion of the linear capacitor.

13. The method as recited in claim 9 wherein forming a linear capacitor includes forming a linear capacitor that has an overlap capacitance substantially greater than a capacitance of the switch.

14. The method as recited in claim 13 wherein forming the linear capacitor includes forming a first electrode, source and drain regions, a gate dielectric located over the source and drain regions, and a serpentine second electrode located on the gate dielectric that overlaps the source and drain regions and the first electrode.

15. The method as recited in claim 14 wherein forming a second electrode includes forming a floating gate for the memory cell.

16. The method as recited in claim 9 further comprising forming a gate oxide having a thickness of about 10 NM.

18. The integrated circuit as recited in claim 17 further comprising an erase input that is connected to the switch.

19. The integrated circuit as recited in claim 17 wherein the voltage transfer structure further comprises a non-linear capacitor connected in series with the control input and the switch and in parallel with the linear capacitor.

20. The integrated circuit as recited in claim 29 wherein the non-linear capacitor forms a portion of the linear capacitor.

21. The integrated circuit as recited in claim 17 wherein the linear capacitor has an overlap capacitance substantially greater than a capacitance of the switch.

22. The integrated circuit as recited in claim 21 wherein the linear capacitor has a first electrode and the linear capacitor includes source and drain regions, a gate dielectric located over the source and drain regions, and a serpentine second electrode located on the gate dielectric that overlaps the source and drain regions and the first electrode.

23. The integrated circuit cell as recited in claim 22 wherein the second electrode forms a floating gate for the memory cell.

24. The integrated circuit as recited in claim 17 further including a gate oxide having a thickness of about 10 NM.

26. The method as recited in claim 25 further comprising forming an erase input that is electrically connected to the switch.

27. The method as recited in claim 25 further comprising forming a non-linear capacitor in series with the control input and the switch and in parallel with the linear capacitor.

28. The method as recited in claim 27 wherein forming the non-linear capacitor includes forming a portion of the linear capacitor.

29. The method as recited in claim 25 wherein forming a linear capacitor includes forming a linear capacitor that has an overlap capacitance substantially greater than a capacitance of the switch.

30. The method as recited in claim 29 wherein forming the linear capacitor includes forming a first electrode, source and drain regions, a gate dielectric located over the source and drain regions, and a serpentine second electrode located on the gate dielectric that overlaps the source and drain regions and the first electrode.

31. The method as recited in claim 30 wherein forming a second electrode includes forming a floating gate for the memory cell.

32. The method as recited in claim 25 further comprising forming a gate oxide having a thickness of about 10 NM.

17. An integrated circuit having an programable read-only-memory (PROM), comprising:

transistors;

memory cells with at least one of the memory cells including;

a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch; and

interconnects that connect the transistors and the memory cells to form an operative integrated circuit.

25. A method of fabricating an integrated circuit having an programmable read-only-memory (PROM), comprising:

forming transistors;

forming memory cells with at least one of the memory cells including;

forming a voltage transfer structure, including;

forming a linear capacitor that electrically couples the control input to the switch; and

forming interconnects that electrically connect the transistors and the memory cells to form an operative integrated circuit.

33. A programmable read only memory (EPROM) cell, comprising:

a control input;

a metal oxide semiconductor (MOS) transistor switch device;

a floating gate, which serves as a gate of the MOS switch device; and

a voltage transfer structure connected to the control input wherein the voltage transfer structure includes a metal oxide semiconductor capacitor with source/drain to gate overlap capacitance that is substantially greater than a capacitance of a floating gate within the switch transistor and wherein the floating gate functions as a gate of the voltage transfer structure MOS capacitor.

34. The memory cell as recited in claim 33 further including an erase input and an erase device connected to the erase input wherein the erase device is a MOS device for the injection of charge onto the floating gate, and wherein the floating gate is the gate of the MOS erase device.

35. The memory cell as recited in claim 33 wherein the source/drain to gate overlap capacitance is at least five times as great as the sum of a floating gate to source/drain area capacitance within the switch transistor and floating gate to substrate capacitances.

36. The memory cell as recited in claim 33 wherein the portion has a serpentine physical layout pattern.

37. The memory cell as recited in claim 36 wherein the portion has a comb physical layout pattern.

38. The memory cell as recited in claim 33 wherein the memory cell is a erasable PROM (EPROM).

39. The memory cell as recited in claim 33 wherein the memory cell is a electrically erasable PROM (EEPROM).

40. The memory cell as recited in claim 33 wherein the memory cell is a flash electrically erasable PROM (flash EPROM).

41. A programmable read only memory (EPROM) cell, comprising:

a control input;

a metal oxide semiconductor (MOS) transistor switch device;

a floating gate that serves as a gate of the MOS switch device; and

a voltage transfer structure connected to the control input wherein the voltage transfer structure includes a linear capacitor with one terminal connected to a control input and another terminal connected to the floating gate and having a capacitance substantially greater than a capacitance of the floating gate.

42. The memory cell as recited in claim 41 wherein the linear capacitor has a first electrode that forms a part of the floating gate and a second electrode that includes a metal plate separated from the floating gate by a dielectric insulator and where the second electrode is connected to the control input.

43. The memory cell as recited in claim 41 wherein the linear capacitor has a first electrode that forms a part of the floating gate and a second electrode that is a well structure separated from the floating gate by a dielectric insulator and where the second electrode is connected to the control input.

44. The memory cell as recited in claim 41 further including an erase input and an erase device connected to the erase input wherein the erase device is a MOS device for the injection of charge onto the floating gate, and wherein the floating gate is a gate of the MOS erase device.

45. The memory cell as recited in claim 41 wherein the linear capacitor has a capacitance at least five times as great as the sum of a floating gate to source/drain area capacitance within the switch transistor and floating gate to substrate capacitances.

46. The memory cell as recited in claim 41 wherein the memory cell is a erasable PROM (EPROM).

47. The memory cell as recited in claim 41 wherein the memory cell is a electrically erasable PROM (EEPROM).

48. The memory cell as recited in claim 41 wherein the memory cell is a flash electrically erasable PROM (flash EPROM).