METHOD FOR COMPLEMENTARY OXIDE TRANSISTOR FABRICATION

• US 20020016030A1
• Filed: 05/07/1999
• Published: 02/07/2002
• Est. Priority Date: 05/07/1999
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: SCHROTT, ALEJANDRO G., MISEWICH, JAMES A., SCOTT, BRUCE A.
• Granted Patent: US 6,479,847 B2
• Time in Patent Office: Days
• US Class Current: 438/199
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H10N 99/03 Devices using Mott metal-insulator transition, e.g. field-effect transistor-like devices

Abstract

A method of manufacturing an integrated circuit device includes forming a laminated structure having a first side and a second side, the first side includes a first type Mott channel layer and the second side includes a second type Mott channel layer. A first source region and a first drain region is formed on the first side, a second source region and a second drain region is formed on the second side, a first gate region is formed on the second side, opposite the first source region and the first drain region and a second gate region is formed on the first side, opposite the second source region and the second drain region. The first source, the first drain and the first gate comprise a first type field effect transistor and the second source, the second drain and the second gate comprise a second type field effect transistor.

Claims

1. A method of manufacturing a complementary field effect transistor structure comprising:

forming a first type Mott channel layer; and

forming a second type Mott channel layer adjacent said first type Mott channel layer,

wherein said first type Mott channel layer is complementary to said second type Mott channel layer.

2. The method in claim 1, further comprising:

forming a first source region, a first drain region and a first gate conductor region adjacent said first type Mott channel layer; and

forming a second source region, a second drain region and a second gate conductor region adjacent said second type Mott channel layer;

wherein said first source region, said first drain region, said first gate conductor region and said first Mott channel layer comprise a first type field effect transistor; and

wherein said second source region, said second drain region, said second gate conductor region and said second type Mott channel layer comprise a second type field effect transistor electrically connected to said first type field effect transistor.

3. The method in claim 2, wherein said forming of said first source region and said first drain region comprises:

forming a first conductive layer adjacent said first type Mott channel layer; and

forming a first insulator region in said first conductive layer opposite said first gate conductor,

said first source region and said first drain region being regions in said first conductive layer on opposite sides of said first insulator region.

4. The method in claim 3, wherein said forming of said second source region and said second drain region comprises:

forming a second conductive layer adjacent said second type Mott channel layer; and

forming a second insulator region in said second conductive layer opposite said second gate conductor,

said second source region and said second drain region being regions in said second conductive layer on opposite sides of said second insulator region.

5. The method in claim 4, wherein said forming of said first gate conductor region and said forming of said second gate conductor region comprise:

forming a gate conductor layer insulated from and positioned between said first type Mott channel layer and said second type Mott channel layer, said first conductive layer and said second conductive layer respectively being on opposite sides of said first type Mott channel layer and said second type Mott channel layer from said gate conductor layer; and

forming a plurality of insulator regions in said gate conductor layer,

wherein said first gate conductor region is a region of said gate conductor layer between two of said insulator regions and is positioned opposite and between said first source region and said first drain region; and

wherein said second gate conductor region is a region of said gate conductor layer between two of said insulator regions and is positioned opposite and between said second source region and said second drain region.

6. The method in claim 5, further comprising:

forming a first conductive oxide layer as said first conductive layer;

forming said first type Mott transition layer on said first conductive oxide layer;

forming a first gate insulator layer on said first type Mott channel layer;

forming a second conductive oxide layer as said gate conductor layer on said first gate insulator layer;

forming a second gate insulator layer on said second conductive oxide layer;

forming said second type Mott channel layer on said second gate insulator layer; and

forming a third conductive oxide layer as said second conductive layer on said second type Mott channel layer.

7. The method in claim 1, wherein said first type Mott channel layer and said second type Mott channel layer change conductivity in the presence of an electric field.

8. The method in claim 2, further comprising connecting said first type field effect transistor and said second type field effect transistor to form said complementary field effect transistor.

9. A method of manufacturing a complementary field effect transistor structure comprising:

forming a laminated structure having a first side and a second side, said first side including a first type Mott channel layer and said second side including a second type Mott channel layer;

forming a first source region and a first drain region in a first conductive layer on said first side;

forming a second source region and a second drain region in a second conductive layer on said second side; and

forming a first gate conductor region and a second gate conductor region in a gate conductor layer positioned between and insulated from said first type Mott channel layer and said second type Mott channel layer,

wherein said first source region, said first drain region, said first gate conductor region and said first type Mott channel layer comprise a first type field effect transistor and said second source region, said second drain region, said second gate conductor region and said second type Mott channel layer comprise a second type field effect transistor.

10. The method in claim 9, wherein said forming of said first source region and said first drain region comprises:

forming a first conductive layer adjacent said first type Mott channel layer; and

forming a first insulator region in said first conductive layer opposite said first gate conductor,

said first source region and said first drain region being regions in said first conductive layer on opposite sides of said first insulator region.

11. The method in claim 10, wherein said forming of said second source region and said second drain region comprises:

forming a second conductive layer adjacent said second type Mott channel layer; and

forming a second insulator region in said second conductive layer opposite said second gate conductor,

said second source region and said second drain region being regions in said second conductive layer on opposite sides of said second insulator region.

12. The method in claim 11, wherein said forming of said first gate conductor region and said forming of said second gate conductor region comprise:

forming a gate conductor layer insulated from and positioned between said first type Mott channel layer and said second type Mott channel layer, said first conductive layer and said second conductive layer respectively being on opposite sides of said first type Mott channel layer and said second type Mott channel layer from said gate conductor layer; and

forming a plurality of insulator regions in said gate conductor layer,

wherein said first gate conductor region is a region of said gate conductor layer between two of said insulator regions and is positioned opposite and between said first source region and said first drain region; and

wherein said second gate conductor region is a region of said gate conductor layer between two of said insulator regions and is positioned opposite and between said second source region and said second drain region.

13. The method in claim 12, wherein said forming of said laminated structure comprises:

forming a first conductive oxide layer as said first conductive layer;

forming said first type Mott transition layer on said first conductive oxide layer;

forming a first gate insulator layer on said first type Mott channel layer;

forming a second conductive oxide layer as said gate conductor layer on said first gate insulator layer;

forming a second gate insulator layer on said second conductive oxide layer;

forming said second type Mott channel layer on said second gate insulator layer; and

forming a third conductive oxide layer as said second conductive layer on said second type Mott channel layer.

14. The method in claim 9, wherein said first type Mott channel layer and said second type Mott channel layer change conductivity in the presence of an electric field.

15. The method in claim 9, further comprising connecting said first type field effect transistor and said second type field effect transistor to form said complementary field effect transistor.

17. The method in claim 16, wherein said first type Mott channel layer and said second type Mott channel layer change conductivity in the presence of an electric field.

18. The method in claim 16, wherein said first type Mott channel layer and said second type Mott channel layer comprise complementary channel regions of a complementary field effect transistor.

19. The method in claim 16, further comprising:

forming a first drain region and a first source region connected to said first type Mott channel layer;

forming a first gate conductor region adjacent said first type Mott channel layer;

forming a second drain region and a second source region connected to said second type Mott channel layer; and

forming a second gate conductor region adjacent said second type Mott channel layer,

wherein said first source region, said first drain region, said first gate conductor region and said first type Mott channel layer comprise a first type field effect transistor and said second source region, said second drain region, said second gate conductor region and said second type Mott channel layer comprise a second type field effect transistor.

16. A method of manufacturing a complementary field effect transistor structure comprising:

forming a first type Mott channel layer over a first portion of a substrate; and

forming a second type Mott channel layer over a second portion of said substrate;

wherein said first type Mott channel layer is complementary to said second type Mott channel layer.

20. A method of forming an integrated circuit device comprising:

forming a release layer on a substrate;

removing a first portion of said release layer to expose a first portion of said substrate and to allow a second portion of said release layer to remain;

forming a first portion of a first type Mott channel layer over said first portion of said substrate and a second portion of said first type Mott channel layer over said second portion of said release layer;

forming a first portion of a first insulator layer over said first portion of said first type Mott channel layer and a second portion of said first insulator layer over said second portion of said first type Mott channel layer;

removing said second portion of said release layer to release said second portion of said Mott channel layer and said second portion of said first insulator layer and to expose said second portion of said substrate;

forming a first portion of a second type Mott channel layer over said first portion of said first insulator layer and forming a second portion of said second type Mott channel layer over said second portion of said substrate;

forming a first portion of a second insulator layer over said first portion of said second type Mott channel layer and a second portion of said second insulator layer over said second portion of said second type Mott channel layer; and

removing said first portion of said second insulator and said first portion of said second type Mott channel layer.

21. The method in claim 20, further comprising, before said removing of said second portion of said release layer, forming a via between:

said first portion of said first insulator and said first portion of said first type Mott channel layer; and

said second portion of said first insulator, said second portion of said first type Mott channel layer and said second portion of said release layer.

22. The method in claim 20, wherein said first type Mott channel layer and said second type Mott channel layer change conductivity in the presence of an electric field.

23. The method in claim 20, wherein said first type Mott channel layer and said second type Mott channel layer comprise complementary channel regions of a complementary field effect transistor.

24. The method in claim 20, wherein said removing of said first portion of said second insulator and said first portion of said second type Mott channel layer comprises one of, dry lithographic patterned etching, wet lithographic patterned etching and chemical mechanical polishing.

26. The structure in claim 25, further comprising:

a first source region, a first drain region and a first gate conductor region adjacent said first type Mott channel layer; and

a second source region, a second drain region and a second gate conductor region adjacent said second type Mott channel layer;

wherein said first source region, said first drain region, said first gate conductor region and said first Mott channel layer comprise a first type field effect transistor; and

wherein said second source region, said second drain region, said second gate conductor region and said second type Mott channel layer comprise a second type field effect transistor electrically connected to said first type field effect transistor.

27. The structure in claim 26, wherein said first source region and said first drain region comprise:

a first conductive layer adjacent said first type Mott channel layer; and

a first insulator region in said first conductive layer opposite said first gate conductor,

said first source region and said first drain region being regions in said first conductive layer on opposite sides of said first insulator region.

28. The structure in claim 27, wherein said second source region and said second drain region comprise:

a second conductive layer adjacent said second type Mott channel layer; and

a second insulator region in said second conductive layer opposite said second gate conductor,

said second source region and said second drain region being regions in said second conductive layer on opposite sides of said second insulator region.

29. The structure in claim 27, wherein said first gate conductor region and said second gate conductor region comprise:

a gate conductor layer insulated from and positioned between said first type Mott channel layer and said second type Mott channel layer, said first conductive layer and said second conductive layer respectively being on opposite sides of said first type Mott channel layer and said second type Mott channel layer from said gate conductor layer; and

a plurality of insulator regions in said gate conductor layer,

wherein said first gate conductor region is a region of said gate conductor layer between two of said insulator regions and is positioned opposite and between said first source region and said first drain region; and

wherein said second gate conductor region is a region of said gate conductor layer between two of said insulator regions and is positioned opposite and between said second source region and said second drain region.

30. The structure in claim 29, wherein said first conductive layer, said second conductive layer and said gate conductor layer comprise conductive oxide layers, and said first type Mott transition layer is positioned on said first conductive layer;

said structure further comprising;

a first gate insulator layer positioned on said first type Mott channel layer, said gate conductor layer being positioned on said first gate insulator layer;

a second gate insulator layer positioned on said gate conductor layer, said second type Mott channel layer being positioned on said second gate insulator layer, and said second conductive layer being positioned on said second type Mott channel layer.

31. The structure in claim 25, wherein said first type Mott channel layer and said second type Mott channel layer change conductivity in the presence of an electric field.

32. The structure in claim 26, wherein said first type field effect transistor and said second type field effect transistor are connected to form said complementary field effect transistor.

25. A complementary field effect structure comprising:

a first type Mott channel layer; and

a second type Mott channel layer adjacent said first type Mott channel layer,

wherein said first type Mott channel layer is complementary to said second type Mott channel layer.

33. A complementary field effect transistor structure comprising:

a laminated structure having a first side and a second side, said first side including a first type Mott channel layer and said second side including a second type Mott channel layer;

a first conductive layer on said first side having a first source region and a first drain region;

a second conductive layer on said second side having a second source region and a second drain region; and

a gate conductor layer positioned between and insulated from said first type Mott channel layer and said second type Mott channel layer, said gate conductor layer having a first gate conductor region and a second gate conductor region,

wherein said first source region, said first drain region, said first gate conductor region and said first type Mott channel layer comprise a first type field effect transistor and said second source region, said second drain region, said second gate conductor region and said second type Mott channel layer comprise a second type field effect transistor.

34. The structure in claim 33, wherein said first source region and said first drain region comprise:

a first conductive layer adjacent said first type Mott channel layer; and

a first insulator region in said first conductive layer opposite said first gate conductor,

said first source region and said first drain region being regions in said first conductive layer on opposite sides of said first insulator region.

35. The structure in claim 34, wherein said second source region and said second drain region comprise:

a second conductive layer adjacent said second type Mott channel layer; and

a second insulator region in said second conductive layer opposite said second gate conductor,

said second source region and said second drain region being regions in said second conductive layer on opposite sides of said second insulator region.

36. The structure in claim 35, wherein said first gate conductor region and said second gate conductor region comprise:

a gate conductor layer insulated from and positioned between said first type Mott channel layer and said second type Mott channel layer, said first conductive layer and said second conductive layer respectively being on opposite sides of said first type Mott channel layer and said second type Mott channel layer from said gate conductor layer; and

a plurality of insulator regions in said gate conductor layer,

wherein said first gate conductor region is a region of said gate conductor layer between two of said insulator regions and is positioned opposite and between said first source region and said first drain region; and

wherein said second gate conductor region is a region of said gate conductor layer between two of said insulator regions and is positioned opposite and between said second source region and said second drain region.

37. The structure in claim 36, wherein said first conductive layer, said second conductive layer and said gate conductor layer comprise conductive oxide layers, and said first type Mott transition layer is positioned on said first conductive layer;

said structure further comprising;

a first gate insulator layer positioned on said first type Mott channel layer, said gate conductor layer being positioned on said first gate insulator layer;

a second gate insulator layer positioned on said gate conductor layer, said second type Mott channel layer being positioned on said second gate insulator layer, and said second conductive layer being positioned on said second type Mott channel layer.

38. The structure in claim 33, wherein said first type Mott channel layer and said second type Mott channel layer change conductivity in the presence of an electric field.

39. The structure in claim 33, wherein said first type field effect transistor and said second type field effect transistor are connected to form said complementary field effect transistor.

40. A complementary field effect transistor structure comprising:

a substrate having first and second portions;

a first type Mott channel layer positioned over said first portion of said substrate; and

a second type Mott channel layer positioned over said second portion of said substrate;

wherein said first type Mott channel layer is complementary to said second type Mott channel layer.

41. The structure in claim 40, wherein said first type Mott channel layer and said second type Mott channel layer change conductivity in the presence of an electric field.

42. The structure in claim 40, wherein said first type Mott channel layer and said second type Mott channel layer comprise complementary channel regions of a complementary field effect transistor.

43. The structure in claim 40, further comprising:

a first drain region and a first source region connected to said first type Mott channel layer;

a first gate conductor region adjacent said first type Mott channel layer;

a second drain region and a second source region connected to said second type Mott channel layer; and

a second gate conductor region adjacent said second type Mott channel layer,

wherein said first source region, said first drain region, said first gate conductor region and said first type Mott channel layer comprise a first type field effect transistor, and said second source region, said second drain region, said second gate conductor region and said second type Mott channel layer comprise a second type field effect transistor.