Method of manufacturing a contact hole of a semiconductor device

• US 20020016077A1
• Filed: 07/27/2001
• Published: 02/07/2002
• Est. Priority Date: 07/28/2000
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Yun, Hwangbo, Young, Lee, Hyuck-Jun
• Granted Patent: US 6,613,683 B2
• Time in Patent Office: Days
• US Class Current: 438/706
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A spacer is formed on a side wall of a gate electrode formed over a substrate, and a dielectric interlayer is then formed over the substrate, the gate electrode and the spacer. A region of the dielectric interlayer is then subjected to a first etching process using an etching gas. An emission amount of a chemical compound emitted during the first etching process is detected, where the chemical compound is produced by a chemical reaction of the etching gas and the spacer. The region of the dielectric interlayer is then subjected to a second etching process upon detecting that the emission amount of the chemical compound has reached a given level. The second etching process may be continued until a contact hole is defined in the dielectric interlayer.

Claims

1. A method of manufacturing a contact hole of a semiconductor device, comprising;

forming a spacer on a side wall of a gate electrode formed over a substrate;

forming a dielectric interlayer over the substrate, the gate electrode and the spacer;

subjecting a region of the dielectric interlayer to a first etching process using an etching gas;

detecting an emission amount of a chemical compound emitted during the first etching process, wherein the chemical compound is produced by a chemical combination of the etching gas and the spacer; and

subjecting the region of the dielectric interlayer to a second etching process upon detecting that the emission amount of the chemical compound has reached a given level.

2. The method as claimed in claim 1, wherein the given level is a maximum level of the emission amount of the chemical compound.

3. The method as claimed in claim 1, further comprising detecting the emission amount of the chemical compound during the second etching process, and terminating the second etching process upon detecting that the amount of the chemical compound during the second etching process has reached a second given level.

4. The method as claimed in claim 1, wherein the dielectric interlayer is comprised of an oxide compound and the spacer is comprised of a nitride compound.

5. The method as claimed in claim 1, wherein the dielectric interlayer is comprised of BPSG (borophosphorus silicate glass) and the spacer is comprised of silicon nitride.

6. The method as claimed in claim 1, wherein the etching gas is at least one selected from the group consisting of C₃F₈, C₄F₈, C₅F₈, and CO.

7. The method as claimed in claim 1, wherein the etching gas and the spacer react to produce the chemical compound having a C—

N bond.

8. A method of manufacturing a contact hole of a semiconductor device, comprising:

forming a spacer on a side wall of a gate electrode formed over a substrate;

forming a stopper layer on an exposed portion of the substrate;

forming a dielectric interlayer over the substrate, the gate electrode, the stopper layer and the spacer;

subjecting a region of the dielectric interlayer to a first etching process using an etching gas;

detecting an emission amount of a chemical compound emitted during the first etching process, wherein the chemical compound is produced by a chemical reaction of the etching gas and the spacer; and

subjecting the region of the dielectric interlayer to a second etching process upon detecting that the emission amount of the chemical compound has reached a given level.

9. The method as claimed in claim 8, wherein the given level is a maximum level of the emission amount of the chemical compound.

10. The method as claimed in claim 8, wherein the dielectric interlayer is comprised of an oxide compound, and the spacer and the stopper layer are comprised of a nitride compound.

11. The method as claimed in claim 8, wherein the dielectric interlayer is comprised of BPSG (borophosphorous silicate glass), and the spacer and the stopper layer are comprised of silicon nitride.

12. The method as claimed in claim 8, wherein said etching gas is at least one selected from the group consisting of C₃F₈, C₄F₈, C₅F₈, and CO.

13. The method as claimed in claim 8, further comprising detecting the emission amount of a second chemical compound during the second etching process, wherein the second chemical compound is produced by a chemical reaction of the etching gas and the stopper layer, and terminating the second etching process upon detecting that the amount of the second chemical compound during the second etching process has reached a second given level.

14. The method as claimed in claim 13, further comprising removing the stopper layer after terminating the second etching process.

15. The method as claimed in claim 14, wherein the chemical compound and the second chemical compound are the same.