LOW-CAPACITANCE BONDING PAD FOR SEMICONDUCTOR DEVICE

• US 20020017672A1
• Filed: 06/09/1999
• Published: 02/14/2002
• Est. Priority Date: 03/19/1999
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: KER, MING-DOU, JIANG, HSIN-CHIN
• Granted Patent: US 6,448,641 B2
• Time in Patent Office: Days
• US Class Current: 257/303
• CPC Class Codes: H01L 2224/02122 being formed on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05012 in top view
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 2224/05095 at the periphery of the internal layers
• CPC Class Codes: H01L 2224/05096 Uniform arrangement, i.e. array
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

Claims

1. A low-capacitance bonding pad structure for a semiconductor device, the structure comprising:

a substrate;

a stacked metal layer positioned on the substrate, wherein the stacked metal layer further comprises a plurality of metal layers and a plurality of dielectric layers, which are alternately stacked up, and the metal layers are coupled by a plurality of via plugs in the dielectric layers;

an uppermost metal layer positioned on the stacked metal layer, wherein an area of each metal layer in the stacked metal layer is smaller than that of the uppermost metal layer; and

a passivation layer having a bonding pad opening positioned on the uppermost metal layer, wherein the bonding pad opening exposes a portion of the uppermost metal layer.

2. The structure of claim 1, wherein the metal layers in the stacked metal layer are in the shape of bars.

3. The structure of claim 2, wherein the bar direction of each layer of the metal layers is across to each other for the different metal layers.

4. The structure of claim 2, wherein the metal layers are stacked and aligned with each other.

5. The structure of claim 1, wherein the metal layers in the stacked metal layer comprises concentric polygons.

6. The structure of claim 1, wherein the metal layers in the stacked metal layer comprises concentric circles.

7. The structure of claim 1, wherein the metal layers in the stacked metal layer comprises a mesh structure.

8. The structure of claim 7, wherein the metal layers in the stacked metal layer are aligned with each other.

9. The structure of claim 7, wherein the mesh is composed of a unit geometric shape.

10. The structure of claim 9, wherein the unit shape is a polygon.

11. The structure of claim 9, wherein the unit shape is a circle.

12. The structure of claim 1, wherein the mesh is composed of various unit shapes.

13. The structure of claim 1, wherein locations of the via plugs in two adjacent layers of the dielectric layers are shifted with a proper distance.

15. The structure of claim 14, wherein the stacked metal layer comprises a plurality of metal layers and a plurality of dielectric layers, which are alternatingly stacked up, and the metal layers are coupled by a plurality of via plugs in the dielectric layers.

16. The structure of claim 14, wherein an area of each metal layer in the stacked metal layer is smaller than that of the uppermost metal layer.

17. The structure of claim 14, wherein the structure further comprises a signal line and a power line between the device and the bonding pad.

18. The structure of claim 17, wherein the stacked metal layer comprises a plurality of metal layers and a plurality of dielectric layers, which are alternatingly stacked up, and the metal layers are coupled by a plurality of via plugs in the dielectric layers.

19. The structure of claim 17, wherein an area of each metal layer in the stacked metal layer is smaller than that of the uppermost metal layer.

20. The structure of claim 14, wherein the device on the substrate just under the bonding pad is an active device.

21. The structure of claim 14, wherein the device on the substrate just under the bonding pad is a passive device.

14. A semiconductor structure, the structure comprising:

a substrate;

a bonding pad over the substrate, wherein the bonding pad comprises a stacked metal layer and an uppermost metal layer; and

a device located on the substrate just under the bonding pad.

22. A low-capacitance bonding pad structure for a semiconductor device, the structure comprising:

a substrate having a well;

a doped region as a diffusion region formed in the well; and

a bonding pad over the substrate and aligned with the doped region, wherein the bonding pad comprises a stacked metal layer and an uppermost metal layer.

23. The structure of claim 22, wherein ions doped in the doped region is opposite to those in the well.

24. The structure of claim 22, wherein the stacked metal layer comprises a plurality of metal layers and a plurality of dielectric layers, which are alternatingly stacked up, and the metal layers are coupled by a plurality of via plugs in the dielectric layers.

25. The structure of claim 22, wherein an area of each metal layer in the stacked metal layer is smaller than that of the uppermost metal layer.